JPS5525515B2 - - Google Patents
Info
- Publication number
- JPS5525515B2 JPS5525515B2 JP7565077A JP7565077A JPS5525515B2 JP S5525515 B2 JPS5525515 B2 JP S5525515B2 JP 7565077 A JP7565077 A JP 7565077A JP 7565077 A JP7565077 A JP 7565077A JP S5525515 B2 JPS5525515 B2 JP S5525515B2
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Memories (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Electrodes Of Semiconductors (AREA)
- Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US05/702,247 US4085498A (en) | 1976-02-09 | 1976-07-02 | Fabrication of integrated circuits containing enhancement-mode FETs and depletion-mode FETs with two layers of polycrystalline silicon utilizing five basic pattern delineating steps |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS535978A JPS535978A (en) | 1978-01-19 |
| JPS5525515B2 true JPS5525515B2 (de) | 1980-07-07 |
Family
ID=24820425
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7565077A Granted JPS535978A (en) | 1976-07-02 | 1977-06-27 | Method of forming enhancement fet and depletion fet |
Country Status (5)
| Country | Link |
|---|---|
| JP (1) | JPS535978A (de) |
| CA (1) | CA1088676A (de) |
| DE (1) | DE2723254A1 (de) |
| GB (1) | GB1522294A (de) |
| IT (1) | IT1113770B (de) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4240092A (en) * | 1976-09-13 | 1980-12-16 | Texas Instruments Incorporated | Random access memory cell with different capacitor and transistor oxide thickness |
| GB2199694A (en) * | 1986-12-23 | 1988-07-13 | Philips Electronic Associated | A method of manufacturing a semiconductor device |
-
1977
- 1977-05-24 DE DE19772723254 patent/DE2723254A1/de active Granted
- 1977-06-15 GB GB25028/77A patent/GB1522294A/en not_active Expired
- 1977-06-23 IT IT24970/77A patent/IT1113770B/it active
- 1977-06-27 JP JP7565077A patent/JPS535978A/ja active Granted
- 1977-06-30 CA CA281,849A patent/CA1088676A/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| DE2723254A1 (de) | 1978-01-12 |
| DE2723254C2 (de) | 1987-10-08 |
| IT1113770B (it) | 1986-01-20 |
| CA1088676A (en) | 1980-10-28 |
| GB1522294A (en) | 1978-08-23 |
| JPS535978A (en) | 1978-01-19 |