JPS5523522A - Operation unit - Google Patents
Operation unitInfo
- Publication number
- JPS5523522A JPS5523522A JP9434378A JP9434378A JPS5523522A JP S5523522 A JPS5523522 A JP S5523522A JP 9434378 A JP9434378 A JP 9434378A JP 9434378 A JP9434378 A JP 9434378A JP S5523522 A JPS5523522 A JP S5523522A
- Authority
- JP
- Japan
- Prior art keywords
- ram
- digit
- register
- read
- timing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
PURPOSE: To reduce the bit time of a machine cycle to improve the processing speed by reading an operated number and an operand at the same timing and executing read-write of a RAM in two phases.
CONSTITUTION: At first timing t1 in line address "0", contents "2" of the lowest digit (0th digit) of register B in first RAM 21 are read to first buffer 27, and contents "0" of the lowest digit of register A in second RAM 22 are read to second buffer 28. At timing t2, transfer commands S.a/b and F.a/b are given to gate circuits 29 and 30, and data "2" and "0" stored temporarily in buffers 27 and 28 are sent to adder 31 through gate circuits 29 and 30. Addition result "2" outputted from circuit 31 is written at the 0th digit of register A in RAM 22.
COPYRIGHT: (C)1980,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9434378A JPS5523522A (en) | 1978-08-02 | 1978-08-02 | Operation unit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9434378A JPS5523522A (en) | 1978-08-02 | 1978-08-02 | Operation unit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5523522A true JPS5523522A (en) | 1980-02-20 |
Family
ID=14107634
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9434378A Pending JPS5523522A (en) | 1978-08-02 | 1978-08-02 | Operation unit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5523522A (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5295940A (en) * | 1976-02-09 | 1977-08-12 | Hitachi Ltd | Computer processing control |
JPS52133734A (en) * | 1976-05-01 | 1977-11-09 | Hitachi Ltd | Data processing unit |
-
1978
- 1978-08-02 JP JP9434378A patent/JPS5523522A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5295940A (en) * | 1976-02-09 | 1977-08-12 | Hitachi Ltd | Computer processing control |
JPS52133734A (en) * | 1976-05-01 | 1977-11-09 | Hitachi Ltd | Data processing unit |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPS5621240A (en) | Information processor | |
JPS5743247A (en) | Information processing equipment | |
JPS54107645A (en) | Information processor | |
JPS5530727A (en) | Information processor | |
JPS57121746A (en) | Information processing device | |
JPS5523522A (en) | Operation unit | |
JPS55134442A (en) | Data transfer unit | |
JPS54148439A (en) | Information memory unit | |
JPS5776604A (en) | Numeric controller | |
JPS55122216A (en) | Magnetic card read/write control unit | |
JPS5587359A (en) | Information transfer device | |
JPS5578339A (en) | Multiplication system | |
JPS55101180A (en) | Address extension unit | |
JPS553038A (en) | Microprogram control unit | |
JPS5585945A (en) | Memory unit | |
JPS5499581A (en) | Arrangement decision device | |
JPS5637892A (en) | Memory unit | |
JPS5679353A (en) | Memory bus data transfer method of multiprocessor | |
JPS5638631A (en) | Data transfer apparatus | |
JPS5487131A (en) | Data processor | |
JPS5543603A (en) | Electronic computer | |
JPS5533228A (en) | Arithmetic unit | |
JPS54154949A (en) | Control system for operation processor | |
JPS5633735A (en) | Control device for instruction execution | |
JPS57207942A (en) | Unpacking circuit |