JPS5518131A - Signal binary coding device - Google Patents

Signal binary coding device

Info

Publication number
JPS5518131A
JPS5518131A JP9069378A JP9069378A JPS5518131A JP S5518131 A JPS5518131 A JP S5518131A JP 9069378 A JP9069378 A JP 9069378A JP 9069378 A JP9069378 A JP 9069378A JP S5518131 A JPS5518131 A JP S5518131A
Authority
JP
Japan
Prior art keywords
signal
level
peak
picture signal
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9069378A
Other languages
Japanese (ja)
Inventor
Mikio Onoki
Masaru Kamimura
Hiroshi Mitsuda
Yoshihiro Nagata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP9069378A priority Critical patent/JPS5518131A/en
Publication of JPS5518131A publication Critical patent/JPS5518131A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To ensure a high-fidelity reproduction of the original by using the peak value of the signal level at the area corresponding to the information of the analog picture signal as the background level and then setting the threshold level between the background level and the black peak level of the anglog picture signal.
CONSTITUTION: Analog picture signal (f) is applied to the information detection differential binary coding circuit for differentiation, and the differential value is binary coded by the fixed threshold value. Differential binary coded signal (j) is delayed by the fixed time through delay circuit 2a and 2b to produce signals (k) and (l). Then the sample holding is given at sample holding circuit 4b to signal (o) produced by giving the peak holding to analog picture signal (f) for the video gate period via signal (l). Another sample holding is given to signal (p) at sample holding circuit 4b via signal (k). Thus threshold value (s) is set for binary coding circuit 6 at nearly the intermediate position between signal (q) and the black peak level of the analog picture signal obtained through black level peak holding circuit 5.
COPYRIGHT: (C)1980,JPO&Japio
JP9069378A 1978-07-24 1978-07-24 Signal binary coding device Pending JPS5518131A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9069378A JPS5518131A (en) 1978-07-24 1978-07-24 Signal binary coding device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9069378A JPS5518131A (en) 1978-07-24 1978-07-24 Signal binary coding device

Publications (1)

Publication Number Publication Date
JPS5518131A true JPS5518131A (en) 1980-02-08

Family

ID=14005599

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9069378A Pending JPS5518131A (en) 1978-07-24 1978-07-24 Signal binary coding device

Country Status (1)

Country Link
JP (1) JPS5518131A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5848572A (en) * 1981-09-17 1983-03-22 Matsushita Graphic Commun Syst Inc Automatic contrast compensation circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5848572A (en) * 1981-09-17 1983-03-22 Matsushita Graphic Commun Syst Inc Automatic contrast compensation circuit
JPS6338150B2 (en) * 1981-09-17 1988-07-28 Matsushita Graphic Communic

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