JPS55163684A - Semiconductor memory device - Google Patents

Semiconductor memory device

Info

Publication number
JPS55163684A
JPS55163684A JP6855479A JP6855479A JPS55163684A JP S55163684 A JPS55163684 A JP S55163684A JP 6855479 A JP6855479 A JP 6855479A JP 6855479 A JP6855479 A JP 6855479A JP S55163684 A JPS55163684 A JP S55163684A
Authority
JP
Japan
Prior art keywords
bit line
lines
bit
driver
groups
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6855479A
Other languages
Japanese (ja)
Inventor
Katsuyuki Yamada
Hideaki Isogai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP6855479A priority Critical patent/JPS55163684A/en
Publication of JPS55163684A publication Critical patent/JPS55163684A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/414—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the bipolar type
    • G11C11/416—Read-write [R-W] circuits 

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)

Abstract

PURPOSE:To realize the high-speed reading by selecting the bit line group of the memory cell of matrix formation via the bit line group driver and the intragroup bit line via the bit line driver respectively. CONSTITUTION:The selection is given to the bit line groups composed of bit line B1 formed with two bit lines B1a and B1b which are selected by bit line group selecting driver BD2 and via load resistance R1 and R2 plus selection switch SW1 according to the output of current switch CS and bit line B2 formed with two bit lines B2a and B2b which are connected together with resistances R1 and R2 plus lines La1 and La2 and then selected by switch SW1 each. And bit lines B1 and B2 within the groups are selected via intragroup bit line driver BD1. Then memory cells M11, M21, M12, M22 and others are selected. The memory cells corresponding to other bit line groups are selected in the same way. In such constitution, both the length and the number of the bit lines to be connected are reduced for lines La1, La2, Lb1, Lb2 and others along with the floating capacity reduced. As a result, the high-speed reading is possible even for the high-density cell.
JP6855479A 1979-06-01 1979-06-01 Semiconductor memory device Pending JPS55163684A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6855479A JPS55163684A (en) 1979-06-01 1979-06-01 Semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6855479A JPS55163684A (en) 1979-06-01 1979-06-01 Semiconductor memory device

Publications (1)

Publication Number Publication Date
JPS55163684A true JPS55163684A (en) 1980-12-19

Family

ID=13377088

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6855479A Pending JPS55163684A (en) 1979-06-01 1979-06-01 Semiconductor memory device

Country Status (1)

Country Link
JP (1) JPS55163684A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08273362A (en) * 1995-03-30 1996-10-18 Nec Ic Microcomput Syst Ltd Semiconductor memory
KR100403348B1 (en) * 2001-10-08 2003-11-01 주식회사 하이닉스반도체 Circuit for bit line selection having hierarchical structure
KR100631174B1 (en) 2005-03-31 2006-10-02 주식회사 하이닉스반도체 Data output driver and method

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08273362A (en) * 1995-03-30 1996-10-18 Nec Ic Microcomput Syst Ltd Semiconductor memory
KR100403348B1 (en) * 2001-10-08 2003-11-01 주식회사 하이닉스반도체 Circuit for bit line selection having hierarchical structure
KR100631174B1 (en) 2005-03-31 2006-10-02 주식회사 하이닉스반도체 Data output driver and method
US7339397B2 (en) 2005-03-31 2008-03-04 Hynix Semiconductor Inc. Data output apparatus and method

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