JPS5475937A - Semiconductor memory - Google Patents
Semiconductor memoryInfo
- Publication number
- JPS5475937A JPS5475937A JP14346977A JP14346977A JPS5475937A JP S5475937 A JPS5475937 A JP S5475937A JP 14346977 A JP14346977 A JP 14346977A JP 14346977 A JP14346977 A JP 14346977A JP S5475937 A JPS5475937 A JP S5475937A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- bad
- memory
- decoder
- memory cells
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Static Random-Access Memory (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
PURPOSE: To enable to make a semiconductor memory good one practically even if bad memory cells such as 1 bad bit and 1 bad line exist in a memory array by adding plural preparatory memory cells to the memory array.
CONSTITUTION: The semiconductor memroy is constituted by the memory array which consists of 4096 words × 1 bit RAM and equips memory cells 4a consisting of 4096 pieces and preparatory memory cells 4b consisting of α pieces, line and column decoder circuits 5 and 6, and control circuit 7. At frist, circuits 5 and 6 are driven to investigate which line and column incoude a bad bit cell. For exmaple, when the memory cell selected by (30) of circuit 5 and (35) bad one, the decoder c ircuit which is to select (35) of circuit 6 is of circuit 6 is bad one, the decoder circuit which is to select (35) of circuit 6 is avoided to use and (35') of circuit 6 is selected by applying the same decoder as the decoder circuit to a decoder circuit for preparatory memory cell 4b. Thus, the semiconductor memory can be used as a good one practically.
COPYRIGHT: (C)1979,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP52143469A JPS598920B2 (en) | 1977-11-29 | 1977-11-29 | semiconductor storage device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP52143469A JPS598920B2 (en) | 1977-11-29 | 1977-11-29 | semiconductor storage device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5475937A true JPS5475937A (en) | 1979-06-18 |
JPS598920B2 JPS598920B2 (en) | 1984-02-28 |
Family
ID=15339423
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP52143469A Expired JPS598920B2 (en) | 1977-11-29 | 1977-11-29 | semiconductor storage device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS598920B2 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS56103468A (en) * | 1979-10-26 | 1981-08-18 | Texas Instruments Inc | Floating gate type programmable memory cell and method of manufacturing same |
JPS58205990A (en) * | 1982-05-25 | 1983-12-01 | Matsushita Electric Ind Co Ltd | Address decoder for storage device |
JPS61264599A (en) * | 1985-05-16 | 1986-11-22 | Fujitsu Ltd | Semiconductor memory device |
-
1977
- 1977-11-29 JP JP52143469A patent/JPS598920B2/en not_active Expired
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS56103468A (en) * | 1979-10-26 | 1981-08-18 | Texas Instruments Inc | Floating gate type programmable memory cell and method of manufacturing same |
JPS58205990A (en) * | 1982-05-25 | 1983-12-01 | Matsushita Electric Ind Co Ltd | Address decoder for storage device |
JPS61264599A (en) * | 1985-05-16 | 1986-11-22 | Fujitsu Ltd | Semiconductor memory device |
Also Published As
Publication number | Publication date |
---|---|
JPS598920B2 (en) | 1984-02-28 |
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