JPS55157023A - Input and output control unit - Google Patents

Input and output control unit

Info

Publication number
JPS55157023A
JPS55157023A JP6546979A JP6546979A JPS55157023A JP S55157023 A JPS55157023 A JP S55157023A JP 6546979 A JP6546979 A JP 6546979A JP 6546979 A JP6546979 A JP 6546979A JP S55157023 A JPS55157023 A JP S55157023A
Authority
JP
Japan
Prior art keywords
input
unit
ioc2
control unit
output control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6546979A
Other languages
Japanese (ja)
Inventor
Akio Otani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP6546979A priority Critical patent/JPS55157023A/en
Publication of JPS55157023A publication Critical patent/JPS55157023A/en
Pending legal-status Critical Current

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  • Debugging And Monitoring (AREA)

Abstract

PURPOSE: To speed up the response of status information to open a central processing unit from the input and output unit, by providing the unit status buffer corresponding to each input and output unit in the input and output control unit.
CONSTITUTION: When the command instruction from a CPU1 is received with an input and output control unit IOC2, the IOC2 performs the pickup and analysis of status information related to the IOC2 including the command check immediately and stores the result in a controller status buffer CSB4. After that, the pickup and analysis for the status information of the input and putput unit I/O requiring much time are not directly made, and the content of the unit status buffer USB#K7 fetching in advance the information relating to the designated input and output unit I/O#K11 is read out, and after this and the content of CSB4 are edited into the format designated at an edition circuit 3, response is made to the CPU1.
COPYRIGHT: (C)1980,JPO&Japio
JP6546979A 1979-05-25 1979-05-25 Input and output control unit Pending JPS55157023A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6546979A JPS55157023A (en) 1979-05-25 1979-05-25 Input and output control unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6546979A JPS55157023A (en) 1979-05-25 1979-05-25 Input and output control unit

Publications (1)

Publication Number Publication Date
JPS55157023A true JPS55157023A (en) 1980-12-06

Family

ID=13287998

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6546979A Pending JPS55157023A (en) 1979-05-25 1979-05-25 Input and output control unit

Country Status (1)

Country Link
JP (1) JPS55157023A (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4978452A (en) * 1972-11-29 1974-07-29
JPS5243333A (en) * 1975-10-01 1977-04-05 Hitachi Ltd Information processing device
JPS52119135A (en) * 1976-03-31 1977-10-06 Toshiba Corp Transferring of status
JPS5495133A (en) * 1978-01-13 1979-07-27 Mitsubishi Electric Corp Input/output processing control system

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4978452A (en) * 1972-11-29 1974-07-29
JPS5243333A (en) * 1975-10-01 1977-04-05 Hitachi Ltd Information processing device
JPS52119135A (en) * 1976-03-31 1977-10-06 Toshiba Corp Transferring of status
JPS5495133A (en) * 1978-01-13 1979-07-27 Mitsubishi Electric Corp Input/output processing control system

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