JPS55153118A - Write error detecting system - Google Patents

Write error detecting system

Info

Publication number
JPS55153118A
JPS55153118A JP5947879A JP5947879A JPS55153118A JP S55153118 A JPS55153118 A JP S55153118A JP 5947879 A JP5947879 A JP 5947879A JP 5947879 A JP5947879 A JP 5947879A JP S55153118 A JPS55153118 A JP S55153118A
Authority
JP
Japan
Prior art keywords
read
time
information
errors
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5947879A
Other languages
Japanese (ja)
Inventor
Fumio Akiyoshi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP5947879A priority Critical patent/JPS55153118A/en
Publication of JPS55153118A publication Critical patent/JPS55153118A/en
Pending legal-status Critical Current

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  • Digital Magnetic Recording (AREA)

Abstract

PURPOSE: To improve processing efficiency by setting two kinds of check time to a timer circuit and by considering an error when read information can not be obtained within the 1st set time to be a restorable error when it is read within the next set time or unrestorable error when not.
CONSTITUTION: Write information from host unit 3 is sent to and written by magnetic tape unit 5 by way of bus 2, write control circuit 1 and bus 4. The information is immediately read by a read head and sent to read information checking circuit 7 via bus 6. To the check timer of timer circuit 10, time (C2) and time (C3) following it are set. On receiving signals from timer circuit 10, checking circuit 7 sorts errors when read information can not be read within time C2 into restorable errors when it can be read within following time C2 and unrestorable errors when not, and then sends signals to host unit 3 via bus 8. The processing efficiency, therefore, improves remarkably.
COPYRIGHT: (C)1980,JPO&Japio
JP5947879A 1979-05-14 1979-05-14 Write error detecting system Pending JPS55153118A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5947879A JPS55153118A (en) 1979-05-14 1979-05-14 Write error detecting system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5947879A JPS55153118A (en) 1979-05-14 1979-05-14 Write error detecting system

Publications (1)

Publication Number Publication Date
JPS55153118A true JPS55153118A (en) 1980-11-28

Family

ID=13114444

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5947879A Pending JPS55153118A (en) 1979-05-14 1979-05-14 Write error detecting system

Country Status (1)

Country Link
JP (1) JPS55153118A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS508329A (en) * 1973-05-25 1975-01-28
JPS508328A (en) * 1973-05-28 1975-01-28

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS508329A (en) * 1973-05-25 1975-01-28
JPS508328A (en) * 1973-05-28 1975-01-28

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