JPS55139627A - Skew display circuit - Google Patents

Skew display circuit

Info

Publication number
JPS55139627A
JPS55139627A JP4771279A JP4771279A JPS55139627A JP S55139627 A JPS55139627 A JP S55139627A JP 4771279 A JP4771279 A JP 4771279A JP 4771279 A JP4771279 A JP 4771279A JP S55139627 A JPS55139627 A JP S55139627A
Authority
JP
Japan
Prior art keywords
skew
value
channel
display
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4771279A
Other languages
Japanese (ja)
Inventor
Tsukasa Furuya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP4771279A priority Critical patent/JPS55139627A/en
Publication of JPS55139627A publication Critical patent/JPS55139627A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To display an accurate skew value without reference to memory performance by separating a skew display circuit from a memory for correcting the skew by using the result of a counting circuit as a skew display signal.
CONSTITUTION: Read-out information is counted by counters C1WCn, provided as many as (n), after being input via input terminals I1WIn. When this input information reaches a fixed value or more, an output signal is generated. Output D of AND circuit A which is output when all of output signals of counters C1WCn reach a fixed value or more is returned to each counter for subtraction. Each channel displays the value of the input information number of the channel as a difference in the information number between the fastest channel and lowest channel and the display value is supplied to a higher rank unit. On the basis of the given difference of the information unmber, the higher rank unit can make skew correction. Thus, the accurate skew value can be displayed without reference to the operation or performance of the memory.
COPYRIGHT: (C)1980,JPO&Japio
JP4771279A 1979-04-18 1979-04-18 Skew display circuit Pending JPS55139627A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4771279A JPS55139627A (en) 1979-04-18 1979-04-18 Skew display circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4771279A JPS55139627A (en) 1979-04-18 1979-04-18 Skew display circuit

Publications (1)

Publication Number Publication Date
JPS55139627A true JPS55139627A (en) 1980-10-31

Family

ID=12782911

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4771279A Pending JPS55139627A (en) 1979-04-18 1979-04-18 Skew display circuit

Country Status (1)

Country Link
JP (1) JPS55139627A (en)

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