JPS55137706A - Amplifier - Google Patents
AmplifierInfo
- Publication number
- JPS55137706A JPS55137706A JP4624079A JP4624079A JPS55137706A JP S55137706 A JPS55137706 A JP S55137706A JP 4624079 A JP4624079 A JP 4624079A JP 4624079 A JP4624079 A JP 4624079A JP S55137706 A JPS55137706 A JP S55137706A
- Authority
- JP
- Japan
- Prior art keywords
- amplifier
- input
- level
- input signal
- signal level
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
- H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
- H03F1/0261—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers with control of the polarisation voltage or current, e.g. gliding Class A
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Amplifiers (AREA)
Abstract
PURPOSE:To improve effectively efficiency while keeping the calss A operation, by changing the bias according to the signal level independently of the frequency. CONSTITUTION:One input signal is supplied to a load through the push-pull amplifier circuit of transistors Tr9, 10, and the other is subjected to full-wave rectification in 2, and the output has the peak held by buffer amplifier 4 and capacitor 16. In case of a large instantaneous value of the input signal, diodes D17 and Tr18 are biased reversely to become a cutoff state, and Tr22 is cut off also, and the DC signal level at output terminal 5 of amplifier 4 is not discharged but is held in a level corresponding to the maximum value. When the input signal level becomes a prescribed value or less, D17 and Tr17, 33 are conductive, and the DC potential of terminal 5 is discharged with a high time constant, and this signal gives a bias voltage to the bases of Tr9, 10 through differential amplifier 6. Outputs of Tr10, 11 are fed back negatively to the inversion input of amplifier 6 through differential amplifier 14, thereby changing the bias values equal to Tr10, 11 according to the input level.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4624079A JPS55137706A (en) | 1979-04-16 | 1979-04-16 | Amplifier |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4624079A JPS55137706A (en) | 1979-04-16 | 1979-04-16 | Amplifier |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS55137706A true JPS55137706A (en) | 1980-10-27 |
Family
ID=12741604
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4624079A Pending JPS55137706A (en) | 1979-04-16 | 1979-04-16 | Amplifier |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS55137706A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009058109A (en) * | 2007-09-04 | 2009-03-19 | Yazaki Corp | Locking structure for protector |
-
1979
- 1979-04-16 JP JP4624079A patent/JPS55137706A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009058109A (en) * | 2007-09-04 | 2009-03-19 | Yazaki Corp | Locking structure for protector |
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