JPS55136771A - Gen-lock control circuit for television synchronizing signal generator - Google Patents
Gen-lock control circuit for television synchronizing signal generatorInfo
- Publication number
- JPS55136771A JPS55136771A JP4357779A JP4357779A JPS55136771A JP S55136771 A JPS55136771 A JP S55136771A JP 4357779 A JP4357779 A JP 4357779A JP 4357779 A JP4357779 A JP 4357779A JP S55136771 A JPS55136771 A JP S55136771A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- gen
- lock
- level
- video
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/04—Synchronising
- H04N5/06—Generation of synchronising signals
- H04N5/067—Arrangements or circuits at the transmitter end
- H04N5/073—Arrangements or circuits at the transmitter end for mutually locking plural sources of synchronising signals, e.g. studios or relay stations
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Synchronizing For Television (AREA)
Abstract
PURPOSE:To prevent unreleased gen-lock in case of video interruption of video signal in television relay and noise production, by enabling the gen-lock control even for the nonvideo signal having a given level for the external reference signal. CONSTITUTION:To the input terminal 1, 2, 3, the vertical drive VD signal b to take control timing, gen-lock ON-OFF control signal d externally, and external reference signal c detecting the level of video signal such as field pick up signal with the level detection circuit are respectively inputted. The state of FF4 is sampled after td time with the signal d, by one shot pulse generator 6, and since the td time is greater than the repetitive period t of the VD signal b and smaller than 2t, the gen- lock off operation is made at the repetitive period t of VD signal in normal operation, and in case of abnormal operation, the one shot pulse signal g and the state of FF4 are compared at the NAND circuit 7, the output is fed back to the input terminal 1 of FF4, inverting FF4 and enabling to turn off the gen-lock even with H level of the VD signal.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4357779A JPS55136771A (en) | 1979-04-12 | 1979-04-12 | Gen-lock control circuit for television synchronizing signal generator |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4357779A JPS55136771A (en) | 1979-04-12 | 1979-04-12 | Gen-lock control circuit for television synchronizing signal generator |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS55136771A true JPS55136771A (en) | 1980-10-24 |
Family
ID=12667605
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4357779A Pending JPS55136771A (en) | 1979-04-12 | 1979-04-12 | Gen-lock control circuit for television synchronizing signal generator |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS55136771A (en) |
-
1979
- 1979-04-12 JP JP4357779A patent/JPS55136771A/en active Pending
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