JPS55128949A - Function testing system for communication control unit - Google Patents
Function testing system for communication control unitInfo
- Publication number
- JPS55128949A JPS55128949A JP3677679A JP3677679A JPS55128949A JP S55128949 A JPS55128949 A JP S55128949A JP 3677679 A JP3677679 A JP 3677679A JP 3677679 A JP3677679 A JP 3677679A JP S55128949 A JPS55128949 A JP S55128949A
- Authority
- JP
- Japan
- Prior art keywords
- control unit
- communication control
- clock
- sent
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/24—Testing correct operation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Small-Scale Networks (AREA)
Abstract
PURPOSE:To secure the function test with the single unit of the communication control unit by installing within the communication control unit the clock oscillator of the same frequency as the clock of the monitor device plus the delay memory featuring the equal time to the loop transmission delay time each. CONSTITUTION:When the single unit test mode is designated through the control panel, the clock sent from clock oscillation circuit 8 in the communication control unit is supplied to each part in place of the clock which is sent from the monitor device to repeater 2 via transmission line 1. And the data from control part 4 is sent to transmission part 5 via frame buffer memory 7. The data of the serial bits sent from part 5 is supplied to reception part 3 and then returned to part 4 again. As the delay time of memory 7 is equal to the loop delay time on the transmission line, the artifitial loop is formed within the communication control unit. Thus the data read out of memory 7 can be seen as if it were just on the transmission line. As a result, each block within the communication control unit features nearly the same operation as that of the normal operation, thus enabling the test with the single unit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3677679A JPS55128949A (en) | 1979-03-28 | 1979-03-28 | Function testing system for communication control unit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3677679A JPS55128949A (en) | 1979-03-28 | 1979-03-28 | Function testing system for communication control unit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS55128949A true JPS55128949A (en) | 1980-10-06 |
Family
ID=12479165
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3677679A Pending JPS55128949A (en) | 1979-03-28 | 1979-03-28 | Function testing system for communication control unit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS55128949A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61187444A (en) * | 1985-02-15 | 1986-08-21 | Hitachi Ltd | Method for diagnosing station |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS50134507A (en) * | 1974-04-13 | 1975-10-24 |
-
1979
- 1979-03-28 JP JP3677679A patent/JPS55128949A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS50134507A (en) * | 1974-04-13 | 1975-10-24 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61187444A (en) * | 1985-02-15 | 1986-08-21 | Hitachi Ltd | Method for diagnosing station |
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