JPS55126863A - Frequency measuring method - Google Patents

Frequency measuring method

Info

Publication number
JPS55126863A
JPS55126863A JP3496979A JP3496979A JPS55126863A JP S55126863 A JPS55126863 A JP S55126863A JP 3496979 A JP3496979 A JP 3496979A JP 3496979 A JP3496979 A JP 3496979A JP S55126863 A JPS55126863 A JP S55126863A
Authority
JP
Japan
Prior art keywords
circuit
gate
signal
counting
gates
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3496979A
Other languages
Japanese (ja)
Inventor
Yasuo Saka
Noboru Ueda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP3496979A priority Critical patent/JPS55126863A/en
Publication of JPS55126863A publication Critical patent/JPS55126863A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To measure a frequency economically by a simply-constituted circuit, by generating a gate signal from a clock signal to obtain a reference frequency value of 1×10n and by counting a measured frequency arriving in the gate signal.
CONSTITUTION: A signal from input terminal 1 is waveform-shaped by waveform shaping circuit 2 and supplied to gate 3. At this time, when a pulse is supplied to set terminal 11, flip-flop circuit 9 is inverted and gates 3 and 6 are made open. A clock signal of a reference frequency appears at gate 6 and is counted by counting circuit 7. When the count value reaches a predetermined count value of 10n, decoding circuit 8 sends a pulse out to reset flip-flop circuit 9 and gates 3 and 6 are closed. With gate 3 open, the input signal is counted by counting circuit 13 and decoded by decoding circuit 14, whose output is displayed by number display unit 15.
COPYRIGHT: (C)1980,JPO&Japio
JP3496979A 1979-03-24 1979-03-24 Frequency measuring method Pending JPS55126863A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3496979A JPS55126863A (en) 1979-03-24 1979-03-24 Frequency measuring method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3496979A JPS55126863A (en) 1979-03-24 1979-03-24 Frequency measuring method

Publications (1)

Publication Number Publication Date
JPS55126863A true JPS55126863A (en) 1980-10-01

Family

ID=12428962

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3496979A Pending JPS55126863A (en) 1979-03-24 1979-03-24 Frequency measuring method

Country Status (1)

Country Link
JP (1) JPS55126863A (en)

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