JPS55125641A - Automatic chip selection apparatus - Google Patents

Automatic chip selection apparatus

Info

Publication number
JPS55125641A
JPS55125641A JP3374579A JP3374579A JPS55125641A JP S55125641 A JPS55125641 A JP S55125641A JP 3374579 A JP3374579 A JP 3374579A JP 3374579 A JP3374579 A JP 3374579A JP S55125641 A JPS55125641 A JP S55125641A
Authority
JP
Japan
Prior art keywords
chip
command
signal
image
camera
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3374579A
Other languages
Japanese (ja)
Other versions
JPS6136704B2 (en
Inventor
Masayuki Naruse
Shige Yamada
Isao Tokumaru
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP3374579A priority Critical patent/JPS55125641A/en
Publication of JPS55125641A publication Critical patent/JPS55125641A/en
Publication of JPS6136704B2 publication Critical patent/JPS6136704B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor

Abstract

PURPOSE:To accomplish the quick removal of chips minimizing the image output region with a circuit simplified by obtaining an image of good contrast through a slight lift of the intended chip at the detection of the chip position. CONSTITUTION:A jig on which a semiconductor chip is laid in a matrix array is placed on x, y and theta bases 11. With the command 30, the first chip is positioned 10 at the center of the camera 50 and pushed up 101 with the shaft end, which allows the clear presentation of the chip image alone. The scanning area is set 40 to effect photoelectric conversion of the signal only limited to the minimum area of the chip. The binary signal 60 thus obrained is sent to a change-over circyit 70 to detect 80 the position. After the removal of noises, the signal is compared with the reference information 81 to compute the deviation. The thrust bar lowers 101 to correct the position of the base 11 according to the command 30. Then, the camera 50 is set to produce the output in the area smaller than the circumference of the chip. Then, detecting 90 the binary signal, the chip is ejected 101 according to the command 30 when rejected and sucked away 102 with a nozzle 103.
JP3374579A 1979-03-22 1979-03-22 Automatic chip selection apparatus Granted JPS55125641A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3374579A JPS55125641A (en) 1979-03-22 1979-03-22 Automatic chip selection apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3374579A JPS55125641A (en) 1979-03-22 1979-03-22 Automatic chip selection apparatus

Publications (2)

Publication Number Publication Date
JPS55125641A true JPS55125641A (en) 1980-09-27
JPS6136704B2 JPS6136704B2 (en) 1986-08-20

Family

ID=12394945

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3374579A Granted JPS55125641A (en) 1979-03-22 1979-03-22 Automatic chip selection apparatus

Country Status (1)

Country Link
JP (1) JPS55125641A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5897844A (en) * 1981-12-07 1983-06-10 Shinkawa Ltd Die repacking device
JPS58165339A (en) * 1982-03-26 1983-09-30 Nec Corp Method and device for mounting semiconductor pellet thereof
JPS59211239A (en) * 1983-05-17 1984-11-30 Nec Corp Semiconductor pellet arraying machine
JPS6127652A (en) * 1984-07-18 1986-02-07 Shinkawa Ltd Wafer positioning device
WO2009008839A1 (en) * 2007-07-09 2009-01-15 Generic Power Pte Ltd Die ejector with illuminating unit

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5044953B2 (en) * 2006-03-23 2012-10-10 富士通セミコンダクター株式会社 Inspection apparatus and inspection method for semiconductor device

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5897844A (en) * 1981-12-07 1983-06-10 Shinkawa Ltd Die repacking device
JPS6262053B2 (en) * 1981-12-07 1987-12-24 Shinkawa Kk
JPS58165339A (en) * 1982-03-26 1983-09-30 Nec Corp Method and device for mounting semiconductor pellet thereof
JPH04388B2 (en) * 1982-03-26 1992-01-07 Nippon Electric Co
JPS59211239A (en) * 1983-05-17 1984-11-30 Nec Corp Semiconductor pellet arraying machine
JPS6127652A (en) * 1984-07-18 1986-02-07 Shinkawa Ltd Wafer positioning device
WO2009008839A1 (en) * 2007-07-09 2009-01-15 Generic Power Pte Ltd Die ejector with illuminating unit

Also Published As

Publication number Publication date
JPS6136704B2 (en) 1986-08-20

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