JPS55121758A - Decoder for cyclic code - Google Patents
Decoder for cyclic codeInfo
- Publication number
- JPS55121758A JPS55121758A JP2821779A JP2821779A JPS55121758A JP S55121758 A JPS55121758 A JP S55121758A JP 2821779 A JP2821779 A JP 2821779A JP 2821779 A JP2821779 A JP 2821779A JP S55121758 A JPS55121758 A JP S55121758A
- Authority
- JP
- Japan
- Prior art keywords
- buffer
- comparator
- bit number
- syndrome
- amount equivalent
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
Abstract
PURPOSE:To obtain a decoder for the cyclic code which can perform the decoding by regarding that the zero precedes by the amount equivalent to the smaller bit number in case the information bit number is less than the amount equivalent to 1-block length. CONSTITUTION:Reception input data (a) is delivered via buffer 101 and also applied to syndrome generator 102. The syndrome grown reads out ROM table 104 possessing the error position pattern via address buffer 103. The pattern read out is given to comparator 106 via buffer 105, and the coincidence is obtained with the output of block counter 107 or 111 which is applied via switch circuit 108. And comparator 106 delivers error correction pulse (h). Timing control parts 110 and 112 receive timing signals CP1 and CP2 showing the head and the end of the reception data burst to give the control to counters 107 and 111 as well as to syndrome generator 102 via shortened block control part 113 in order to cope with the shortened signal.
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2821779A JPS55121758A (en) | 1979-03-13 | 1979-03-13 | Decoder for cyclic code |
US06/129,486 US4320511A (en) | 1979-03-13 | 1980-03-11 | Method and device for conversion between a cyclic and a general code sequence by the use of dummy zero bit series |
CA000347495A CA1148660A (en) | 1979-03-13 | 1980-03-12 | Method and device for carrying out conversion between a cyclic and a general code sequence by the use of a hypothetical zero bit series |
GB8008302A GB2050121B (en) | 1979-03-13 | 1980-03-12 | Method and device for carrying out conversion between a cyclic and a general code sequence by the use of a hypothetical zero bit series |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2821779A JPS55121758A (en) | 1979-03-13 | 1979-03-13 | Decoder for cyclic code |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS55121758A true JPS55121758A (en) | 1980-09-19 |
JPS625380B2 JPS625380B2 (en) | 1987-02-04 |
Family
ID=12242455
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2821779A Granted JPS55121758A (en) | 1979-03-13 | 1979-03-13 | Decoder for cyclic code |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS55121758A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01160118A (en) * | 1987-12-16 | 1989-06-23 | Fujitsu Ltd | Bch decoder |
-
1979
- 1979-03-13 JP JP2821779A patent/JPS55121758A/en active Granted
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01160118A (en) * | 1987-12-16 | 1989-06-23 | Fujitsu Ltd | Bch decoder |
Also Published As
Publication number | Publication date |
---|---|
JPS625380B2 (en) | 1987-02-04 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
HK118795A (en) | Method and apparatus for decoding error correction code | |
ES436441A1 (en) | Synchronization circuit for a viterbi decoder | |
EP0109551B1 (en) | Apparatus for decoding video address code signals | |
EP0155110A3 (en) | Viterbi decoder comprising a majority circuit in producing a decoded signal | |
JPS55121758A (en) | Decoder for cyclic code | |
CA2371996A1 (en) | Method and system for encoding to mitigate decoding errors in a receiver | |
US5003540A (en) | Error correction coding and decoding circuit for digitally coded information | |
JPS5625853A (en) | Information transmission system | |
JPS52131411A (en) | Decoding and record control system for picture signal | |
JPS5425637A (en) | Memory unit | |
JPS5431266A (en) | Code decoder circuit | |
JPS5717265A (en) | Facsimile recording and control system | |
ES8200983A1 (en) | Improved Error Coding for Video Disc System | |
JPS5766597A (en) | Error correction circuit | |
EP0254279A3 (en) | Rotary head type recording and/or reproducing apparatus | |
JPS5930342B2 (en) | Transmission/reception switching method of transmitting/receiving shared code decoder | |
JPS55136753A (en) | Compressed data recovery system | |
JPS5457848A (en) | Detecting correction system for block error | |
JPS54104315A (en) | Forming method of coded signals | |
JPS5330214A (en) | Encoding transmission system for picture signal | |
JPS53108242A (en) | Memory device | |
JPS53108728A (en) | Optical character reader | |
DE69931641D1 (en) | PROCESS FOR CODING INFORMATION SIGNALS | |
JPS5680973A (en) | Signal decoding system | |
JPS6416028A (en) | Decoding system for error correction block code |