JPS6416028A - Decoding system for error correction block code - Google Patents
Decoding system for error correction block codeInfo
- Publication number
- JPS6416028A JPS6416028A JP62169875A JP16987587A JPS6416028A JP S6416028 A JPS6416028 A JP S6416028A JP 62169875 A JP62169875 A JP 62169875A JP 16987587 A JP16987587 A JP 16987587A JP S6416028 A JPS6416028 A JP S6416028A
- Authority
- JP
- Japan
- Prior art keywords
- rate
- error
- rejection
- quality information
- component
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Error Detection And Correction (AREA)
- Detection And Prevention Of Errors In Transmission (AREA)
- Detection And Correction Of Errors (AREA)
Abstract
PURPOSE:To increase the degree of freedom for setting the distribution rate of a mis-reception rate and a critical rate by deciding the acceptance/rejection of a decoded word output corresponding to the combination between an erroneous pattern and quality information. CONSTITUTION:An error pattern E consists of sets of error component ei of each component ri of a received word R and a quality information register 3 receives the quality information qi corresponding to each component ri of the received word, stores it and outputs the quality information Q. Then a critical region circuit 5 outputs A=1 (rejection) when the logical state of ei=0 (no error) and qi=1 (quality deterioration) takes place at least one symbol position (i) so as to detect the rejection condition due to the production of the quality deterioration information not included in the symbol location representing an error. Thus, either the rejection rate of the code or the mis- acceptance rate is set continuously in a prescribed range, and the degree of the freedom of the distribution rate setting of the both is improved.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62169875A JP2547577B2 (en) | 1987-07-09 | 1987-07-09 | Error correction block code decoding method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62169875A JP2547577B2 (en) | 1987-07-09 | 1987-07-09 | Error correction block code decoding method |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6416028A true JPS6416028A (en) | 1989-01-19 |
JP2547577B2 JP2547577B2 (en) | 1996-10-23 |
Family
ID=15894577
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62169875A Expired - Fee Related JP2547577B2 (en) | 1987-07-09 | 1987-07-09 | Error correction block code decoding method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2547577B2 (en) |
-
1987
- 1987-07-09 JP JP62169875A patent/JP2547577B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP2547577B2 (en) | 1996-10-23 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
LAPS | Cancellation because of no payment of annual fees |