JPS55121551A - Memory start system of pipeline processing system - Google Patents

Memory start system of pipeline processing system

Info

Publication number
JPS55121551A
JPS55121551A JP2867679A JP2867679A JPS55121551A JP S55121551 A JPS55121551 A JP S55121551A JP 2867679 A JP2867679 A JP 2867679A JP 2867679 A JP2867679 A JP 2867679A JP S55121551 A JPS55121551 A JP S55121551A
Authority
JP
Japan
Prior art keywords
execution
unit
instruction
unit3
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2867679A
Other languages
Japanese (ja)
Inventor
Hiroshi Watanabe
Ryoichi Takamatsu
Tadaaki Bando
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP2867679A priority Critical patent/JPS55121551A/en
Publication of JPS55121551A publication Critical patent/JPS55121551A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To shorten the time of instruction execution of a computer which performs pipeline processing, by deciding on an execution address and setting a memory start signal in an early stage by only a specific instruction, and by reducing the memory access time load on this instruction within its execution time.
CONSTITUTION: Main memory unit 1 is brought under the control of main control unit 2 to transfer data to I-UNIT3 and E-UNIT4. Here, I-UNIT3 consists of instruction decoding unit 6 which generates a microprogram initial address in instruction execution and execution-address arithmetic unit 5 which calculates the execution-address. Then, E-UNIT4 consists of instruction execution unit 7 which executes actual instructions on the basis of the above-mentioned data transferred from I-UNIT3. Further, E-UNIT4 and I-UNIT3 are synchronized with each other through pipeline control unit 8, and the synchronization of the processing is put into effect on the end of each unit.
COPYRIGHT: (C)1980,JPO&Japio
JP2867679A 1979-03-14 1979-03-14 Memory start system of pipeline processing system Pending JPS55121551A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2867679A JPS55121551A (en) 1979-03-14 1979-03-14 Memory start system of pipeline processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2867679A JPS55121551A (en) 1979-03-14 1979-03-14 Memory start system of pipeline processing system

Publications (1)

Publication Number Publication Date
JPS55121551A true JPS55121551A (en) 1980-09-18

Family

ID=12255094

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2867679A Pending JPS55121551A (en) 1979-03-14 1979-03-14 Memory start system of pipeline processing system

Country Status (1)

Country Link
JP (1) JPS55121551A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5024044A (en) * 1973-07-04 1975-03-14
JPS50128949A (en) * 1974-03-29 1975-10-11
JPS50128948A (en) * 1974-03-29 1975-10-11

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5024044A (en) * 1973-07-04 1975-03-14
JPS50128949A (en) * 1974-03-29 1975-10-11
JPS50128948A (en) * 1974-03-29 1975-10-11

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