JPS55121158A - Noise test unit - Google Patents

Noise test unit

Info

Publication number
JPS55121158A
JPS55121158A JP2895079A JP2895079A JPS55121158A JP S55121158 A JPS55121158 A JP S55121158A JP 2895079 A JP2895079 A JP 2895079A JP 2895079 A JP2895079 A JP 2895079A JP S55121158 A JPS55121158 A JP S55121158A
Authority
JP
Japan
Prior art keywords
noise
print board
tested print
generates
pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2895079A
Other languages
Japanese (ja)
Inventor
Yoji Okano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP2895079A priority Critical patent/JPS55121158A/en
Publication of JPS55121158A publication Critical patent/JPS55121158A/en
Pending legal-status Critical Current

Links

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  • Tests Of Electronic Circuits (AREA)

Abstract

PURPOSE: To improve reliability by providing a noise generation means, which generates a flase noise signal, and a noise output means which outputs the false noise signal generated from the noise generation means when no clock is applied.
CONSTITUTION: Input pattern generator 1 generates a test pattern applied to tested print board 10. Expectative pattern generator 2 generates an expectative output pattern, which is the same signal as the output signal obtained according to the test pattern, when the circuit formed in tested print board 10 is normal. When clocks from clock generator 15 are not applied to tested print board 10, the false noise signal from false noise generation circuit 8 is applied to tested print board 10, thus testing whether tested print board 10 is operated for noise or not.
COPYRIGHT: (C)1980,JPO&Japio
JP2895079A 1979-03-13 1979-03-13 Noise test unit Pending JPS55121158A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2895079A JPS55121158A (en) 1979-03-13 1979-03-13 Noise test unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2895079A JPS55121158A (en) 1979-03-13 1979-03-13 Noise test unit

Publications (1)

Publication Number Publication Date
JPS55121158A true JPS55121158A (en) 1980-09-18

Family

ID=12262679

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2895079A Pending JPS55121158A (en) 1979-03-13 1979-03-13 Noise test unit

Country Status (1)

Country Link
JP (1) JPS55121158A (en)

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