JPS55118258A - Frequency selection system - Google Patents

Frequency selection system

Info

Publication number
JPS55118258A
JPS55118258A JP2530879A JP2530879A JPS55118258A JP S55118258 A JPS55118258 A JP S55118258A JP 2530879 A JP2530879 A JP 2530879A JP 2530879 A JP2530879 A JP 2530879A JP S55118258 A JPS55118258 A JP S55118258A
Authority
JP
Japan
Prior art keywords
frequency
oscillator
phase
sets
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2530879A
Other languages
Japanese (ja)
Inventor
Yoshio Takeda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP2530879A priority Critical patent/JPS55118258A/en
Publication of JPS55118258A publication Critical patent/JPS55118258A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/26—Systems using multi-frequency codes

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)

Abstract

PURPOSE:To unify the oscillator and selection circuit, by using the phase locked loop circuit as the frequency oscillation circuit and changing the selective frequency through the use of memory, in the circuit selecting r sets of arbitrary frequencies among n sets of frequencies. CONSTITUTION:nCr code signal (a) and nCr set signal (b) are inputted as the address and chip selection to the read only memory 8 as the frequency selection input and the data of the memory 8 is set as the input to the program counter 7. Next, the self-running frequency output of the voltage controlled oscillator 6 is frequency- divided with the value of the counter 7 and it is given to the phase detector 4 as the phase comparison wave, phase comparison is made with the standard frequency of the main oscillator 3 and control is made so that the phase of the phase comparison wave and the standard wave can be equal with the closed loop of the oscillator 6 and the low pass filter 5. The r sets of selective frequencies have equal stability as the main oscillator 3 after a given time.
JP2530879A 1979-03-05 1979-03-05 Frequency selection system Pending JPS55118258A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2530879A JPS55118258A (en) 1979-03-05 1979-03-05 Frequency selection system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2530879A JPS55118258A (en) 1979-03-05 1979-03-05 Frequency selection system

Publications (1)

Publication Number Publication Date
JPS55118258A true JPS55118258A (en) 1980-09-11

Family

ID=12162370

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2530879A Pending JPS55118258A (en) 1979-03-05 1979-03-05 Frequency selection system

Country Status (1)

Country Link
JP (1) JPS55118258A (en)

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