JPS5511667A - Information transmission system - Google Patents

Information transmission system

Info

Publication number
JPS5511667A
JPS5511667A JP8479578A JP8479578A JPS5511667A JP S5511667 A JPS5511667 A JP S5511667A JP 8479578 A JP8479578 A JP 8479578A JP 8479578 A JP8479578 A JP 8479578A JP S5511667 A JPS5511667 A JP S5511667A
Authority
JP
Japan
Prior art keywords
bit information
parallel
registers
input
information
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8479578A
Other languages
Japanese (ja)
Inventor
Tomoji Ichinose
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP8479578A priority Critical patent/JPS5511667A/en
Publication of JPS5511667A publication Critical patent/JPS5511667A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/16—Time-division multiplex systems in which the time allocation to individual channels within a transmission cycle is variable, e.g. to accommodate varying complexity of signals, to vary number of channels transmitted

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Time-Division Multiplex Systems (AREA)

Abstract

PURPOSE:To increase the transmission velocity for the specified bit information by supplying the specified bit information in parallel into plural units of registers and then transmitting plural units of the specified bit information within a frame. CONSTITUTION:The bit information to be supplied to input terminal (1) of input register 1 is supplied in parallel also into input registers 2 and 3. At the same time, output terminals (1), (11) and (21) of output registers 8-10 are connected in parallel at the reception side. A cyclic selection is given to input registers 1-3, and the parallel information of these input registers are converted into the serial information for transmission. Thus, the bit information supplied to terminal (1) can be transmitted in a speed of three times as high as that of other bit information. As a result, a highly efficient use can be ensured for the transmission line if the number of the specified bit information is set in accordance with the state of the transmission line.
JP8479578A 1978-07-11 1978-07-11 Information transmission system Pending JPS5511667A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8479578A JPS5511667A (en) 1978-07-11 1978-07-11 Information transmission system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8479578A JPS5511667A (en) 1978-07-11 1978-07-11 Information transmission system

Publications (1)

Publication Number Publication Date
JPS5511667A true JPS5511667A (en) 1980-01-26

Family

ID=13840626

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8479578A Pending JPS5511667A (en) 1978-07-11 1978-07-11 Information transmission system

Country Status (1)

Country Link
JP (1) JPS5511667A (en)

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