JPS55107345A - Pilot signal erase system - Google Patents
Pilot signal erase systemInfo
- Publication number
- JPS55107345A JPS55107345A JP1449179A JP1449179A JPS55107345A JP S55107345 A JPS55107345 A JP S55107345A JP 1449179 A JP1449179 A JP 1449179A JP 1449179 A JP1449179 A JP 1449179A JP S55107345 A JPS55107345 A JP S55107345A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- unit
- phase
- fed
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B3/00—Line transmission systems
- H04B3/02—Details
- H04B3/04—Control of transmission; Equalising
- H04B3/10—Control of transmission; Equalising by pilot signal
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
Abstract
PURPOSE:To remove P signal inserted in the signal band or near the signal band with a simple constitution, by controlling the amplitude of pilot P erase signal based on the identified error information of reception signal. CONSTITUTION:The reception signal is divided into two, signal 201 and signal 202, at the distributor 11. The signal 202 is fed to the P signal pickup unit 13, the output of the pickup unit 13 is inputted to the phase synchronizing circuit 14, to produce the P signal inserted to the reception signal and the signal 204 in phase synchronism. The signal 204 is divided into two, one is fed to the amplitude variable unit 15 and another is fed to the variable phase shifter 19. The phase shifter 19 outputs the signal adjusting the input signal to the same phase as the output signal 206 of the coupler 12. This signal is converted into digital signal and latched 23 in the sample timing of the identifying unit 18. The output of the circuit 23 takes corelativity with the identified error signal from the identifying unit 18 at the corelativity unit 21 and fed as the amplitude control voltage of the variable unit 15 with smoothing 20. The output of the variable unit 15 is adjusted to the optimum phase erasing the P signal at the phase shifter 17 and P signal of the signal 201 is rejected at the coupler 12 and outputted.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1449179A JPS55107345A (en) | 1979-02-09 | 1979-02-09 | Pilot signal erase system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1449179A JPS55107345A (en) | 1979-02-09 | 1979-02-09 | Pilot signal erase system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS55107345A true JPS55107345A (en) | 1980-08-18 |
Family
ID=11862514
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1449179A Pending JPS55107345A (en) | 1979-02-09 | 1979-02-09 | Pilot signal erase system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS55107345A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5339132A (en) * | 1991-07-16 | 1994-08-16 | Fujitsu Isotec Limited | Mount structure of a light emitting element array in electronic photographic apparatus |
-
1979
- 1979-02-09 JP JP1449179A patent/JPS55107345A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5339132A (en) * | 1991-07-16 | 1994-08-16 | Fujitsu Isotec Limited | Mount structure of a light emitting element array in electronic photographic apparatus |
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