JPS55105433A - Maximum value memory circuit device - Google Patents

Maximum value memory circuit device

Info

Publication number
JPS55105433A
JPS55105433A JP1298379A JP1298379A JPS55105433A JP S55105433 A JPS55105433 A JP S55105433A JP 1298379 A JP1298379 A JP 1298379A JP 1298379 A JP1298379 A JP 1298379A JP S55105433 A JPS55105433 A JP S55105433A
Authority
JP
Japan
Prior art keywords
maximum value
input
gate
level
maximum
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1298379A
Other languages
Japanese (ja)
Inventor
Takehiko Suzuki
Shigeo Eto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Akashi Seisakusho KK
Original Assignee
Akashi Seisakusho KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Akashi Seisakusho KK filed Critical Akashi Seisakusho KK
Priority to JP1298379A priority Critical patent/JPS55105433A/en
Publication of JPS55105433A publication Critical patent/JPS55105433A/en
Pending legal-status Critical Current

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  • Analogue/Digital Conversion (AREA)

Abstract

PURPOSE: To obtain a high-accuracy maximum value memory circuit featuring the simple constitution by always giving the maximum value to the input comparator as the input of one side.
CONSTITUTION: Input analog signal SC is compared with the maximum volue at maximum value comparison circuit 8, and the signal of the H or L level is applied to gate 9. In case signal SC is larger than the maximum value memorized presently, the output features the H level. And the pulses sent from oscillator 10 are supplied to decimal counter 11 through gate 9 and then counted to renew the maximum value. On the other hand, this count value undergoes the D/A conversion in sequence to be applied sequentially to circuit 8 in the form of the maximum analog quantity. Thus the counting is continued until the input of gate 9 reaches the L level, and accordingly the maximum value can be detected and then memorized in equence regardless of existence of the input signal group.
COPYRIGHT: (C)1980,JPO&Japio
JP1298379A 1979-02-07 1979-02-07 Maximum value memory circuit device Pending JPS55105433A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1298379A JPS55105433A (en) 1979-02-07 1979-02-07 Maximum value memory circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1298379A JPS55105433A (en) 1979-02-07 1979-02-07 Maximum value memory circuit device

Publications (1)

Publication Number Publication Date
JPS55105433A true JPS55105433A (en) 1980-08-13

Family

ID=11820434

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1298379A Pending JPS55105433A (en) 1979-02-07 1979-02-07 Maximum value memory circuit device

Country Status (1)

Country Link
JP (1) JPS55105433A (en)

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