JPS55103677A - Wasteful time generator - Google Patents

Wasteful time generator

Info

Publication number
JPS55103677A
JPS55103677A JP1126879A JP1126879A JPS55103677A JP S55103677 A JPS55103677 A JP S55103677A JP 1126879 A JP1126879 A JP 1126879A JP 1126879 A JP1126879 A JP 1126879A JP S55103677 A JPS55103677 A JP S55103677A
Authority
JP
Japan
Prior art keywords
time
signal
deltax
wasteful
delay
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1126879A
Other languages
Japanese (ja)
Inventor
Kazutaka Osagawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP1126879A priority Critical patent/JPS55103677A/en
Publication of JPS55103677A publication Critical patent/JPS55103677A/en
Pending legal-status Critical Current

Links

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  • Testing And Monitoring For Control Systems (AREA)

Abstract

PURPOSE:To make it possible to give delay to a signal properly according to the mode of a process instrumentation system and output this signal, by converting the analogue input signal to a digital signal to generate arbitrarily a wasteful time digitally. CONSTITUTION:The analogue input signal inputted to input terminal 11 from the external is converted to a digital value by A-D converter 10 and is supplied to succeeding micro processor 12, and here, digital values inputted momentarily are stored at the beginning of table 13' of table size k of RAM 13 as (current read value-preceding read value)=DELTAx. Wasteful time L set arbitrarily by wasteful time generator 14 is inputted to processor 12 and is collated with the time signal of time signal generation part 15 to detect original electric wasteful time L, and micro processor 12 has interrupt period DELTAt to operate k.DELTAt/L; and when DELTAx of table 13' is moved successively by this time to read the sum of DELTAx, digital values are outputted with a delay of time L. Then, the read output is subjected to D-A conversion, so that the input signal may be outputted with a delay of time L.
JP1126879A 1979-02-02 1979-02-02 Wasteful time generator Pending JPS55103677A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1126879A JPS55103677A (en) 1979-02-02 1979-02-02 Wasteful time generator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1126879A JPS55103677A (en) 1979-02-02 1979-02-02 Wasteful time generator

Publications (1)

Publication Number Publication Date
JPS55103677A true JPS55103677A (en) 1980-08-08

Family

ID=11773212

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1126879A Pending JPS55103677A (en) 1979-02-02 1979-02-02 Wasteful time generator

Country Status (1)

Country Link
JP (1) JPS55103677A (en)

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