JPS55100071A - Inverter controlling circuit for pulse width modulation - Google Patents

Inverter controlling circuit for pulse width modulation

Info

Publication number
JPS55100071A
JPS55100071A JP485579A JP485579A JPS55100071A JP S55100071 A JPS55100071 A JP S55100071A JP 485579 A JP485579 A JP 485579A JP 485579 A JP485579 A JP 485579A JP S55100071 A JPS55100071 A JP S55100071A
Authority
JP
Japan
Prior art keywords
reset pulse
signal
pulse width
pulse
width modulation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP485579A
Other languages
Japanese (ja)
Inventor
Nobuyoshi Muto
Yasuo Matsuda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP485579A priority Critical patent/JPS55100071A/en
Publication of JPS55100071A publication Critical patent/JPS55100071A/en
Pending legal-status Critical Current

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  • Inverter Devices (AREA)

Abstract

PURPOSE: To increase a noise margin by a method wherein a reset pulse being set at the lower limit value of an allowable pulse width and a pulse width modulation signal obtained by taking a logical sum with the output signal of a comparator are utilized as a base driving signal of each phase.
CONSTITUTION: A voltage which changes into a linear one at the time when it occurs at a lamp circuit 1 is transformed to a square wave of a variable frequency by a square wave oscillator 2. Further, a reset pulse which determines the time and the point where a pulse height of a saw tooth wave is given, generates at the reset pulse generating circuit 3. The output of the lamp circuit 4 having an upper limiter and after comparing it with a saw tooth wave having a zero duration obtained by guiding the inverted signal of the reset pulse and the reset pulse to a saw tooth wave generating circuit 5 with a comparator, it becomes a pulse width modulation signal. This signal is guided to a logical sum circuit with the reset pulse and a base driving signal in each phase is sent therefrom.
COPYRIGHT: (C)1980,JPO&Japio
JP485579A 1979-01-22 1979-01-22 Inverter controlling circuit for pulse width modulation Pending JPS55100071A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP485579A JPS55100071A (en) 1979-01-22 1979-01-22 Inverter controlling circuit for pulse width modulation

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP485579A JPS55100071A (en) 1979-01-22 1979-01-22 Inverter controlling circuit for pulse width modulation

Publications (1)

Publication Number Publication Date
JPS55100071A true JPS55100071A (en) 1980-07-30

Family

ID=11595285

Family Applications (1)

Application Number Title Priority Date Filing Date
JP485579A Pending JPS55100071A (en) 1979-01-22 1979-01-22 Inverter controlling circuit for pulse width modulation

Country Status (1)

Country Link
JP (1) JPS55100071A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63503372A (en) * 1986-05-20 1988-12-08 エヌシーアール インターナショナル インコーポレイテッド Printer control circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63503372A (en) * 1986-05-20 1988-12-08 エヌシーアール インターナショナル インコーポレイテッド Printer control circuit

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