JPS5494365A - Method of making electronic module for timepiece* and electronic module - Google Patents

Method of making electronic module for timepiece* and electronic module

Info

Publication number
JPS5494365A
JPS5494365A JP15568778A JP15568778A JPS5494365A JP S5494365 A JPS5494365 A JP S5494365A JP 15568778 A JP15568778 A JP 15568778A JP 15568778 A JP15568778 A JP 15568778A JP S5494365 A JPS5494365 A JP S5494365A
Authority
JP
Japan
Prior art keywords
aperture
electronic module
circuit
module
timepiece
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15568778A
Other languages
Japanese (ja)
Inventor
Borutsu Jiyan
Kuro Fuiritsupu
Goree Fuiritsupu
Paratsuto Danieru
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
FONTAINEMELON HORLOGERIE
Original Assignee
FONTAINEMELON HORLOGERIE
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by FONTAINEMELON HORLOGERIE filed Critical FONTAINEMELON HORLOGERIE
Publication of JPS5494365A publication Critical patent/JPS5494365A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • G—PHYSICS
    • G04—HOROLOGY
    • G04C—ELECTROMECHANICAL CLOCKS OR WATCHES
    • G04C3/00—Electromechanical clocks or watches independent of other time-pieces and in which the movement is maintained by electric means
    • G04C3/008—Mounting, assembling of components
    • G—PHYSICS
    • G04—HOROLOGY
    • G04D—APPARATUS OR TOOLS SPECIALLY DESIGNED FOR MAKING OR MAINTAINING CLOCKS OR WATCHES
    • G04D1/00—Gripping, holding, or supporting devices
    • G04D1/005—Gripping, holding, or supporting devices for non-automatic assembly, with automatic transport between workbenches
    • G04D1/0057—Conveyor belts or chains
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49572—Lead-frames or other flat leads consisting of thin flexible metallic tape with or without a film carrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/86—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using tape automated bonding [TAB]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01052—Tellurium [Te]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01057—Lanthanum [La]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01058—Cerium [Ce]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/189—Printed circuits structurally associated with non-printed electric components characterised by the use of a flexible or folded printed circuit

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Electric Clocks (AREA)
  • Electromechanical Clocks (AREA)
  • Credit Cards Or The Like (AREA)
  • Combinations Of Printed Boards (AREA)

Abstract

A through-aperture (3a) is made in the substrate (1) of the module and a conductive layer (4) covering the aperture (3a) is affixed to this substrate. This metal layer is removed at the place where its presence is not desired, so as to produce the network of electrical conductors of the module, and at the same time, metal tags (4c) extending freely above the aperture (3a) are made. The integrated circuit (6) is fitted into the aperture (3a) by placing its terminals (7) opposite the ends of the tags (4c), then the latter are welded to the said terminals. The size of the aperture (3a) is slightly greater than that of the circuit (6) so that the annular free space made between the walls of the aperture (3a) and the said circuit is capillary. The integrated circuit (6) is covered with a polymerisable protective resin (8) which flows at (8a), before its polymerisation, into the said annular space where it is retained by capillarity. <IMAGE>
JP15568778A 1977-12-14 1978-12-14 Method of making electronic module for timepiece* and electronic module Pending JPS5494365A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CH1537777A CH621035GA3 (en) 1977-12-14 1977-12-14 Method of manufacturing an electronic module for timepiece and electronic module obtained by implementing this method

Publications (1)

Publication Number Publication Date
JPS5494365A true JPS5494365A (en) 1979-07-26

Family

ID=4408582

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15568778A Pending JPS5494365A (en) 1977-12-14 1978-12-14 Method of making electronic module for timepiece* and electronic module

Country Status (4)

Country Link
JP (1) JPS5494365A (en)
CH (1) CH621035GA3 (en)
DE (1) DE2854274A1 (en)
FR (1) FR2412226A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3147729A1 (en) * 1981-12-02 1983-06-09 Siemens AG, 1000 Berlin und 8000 München INTERMEDIATE CARRIER TAPE WITH WIRING ELEMENTS FOR FITTING WITH CHIP COMPONENTS

Also Published As

Publication number Publication date
DE2854274A1 (en) 1979-06-28
CH621035B (en) 1900-01-01
FR2412226A1 (en) 1979-07-13
CH621035GA3 (en) 1981-01-15

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