JPS5493950A - Pulse amplifier circuit - Google Patents

Pulse amplifier circuit

Info

Publication number
JPS5493950A
JPS5493950A JP76778A JP76778A JPS5493950A JP S5493950 A JPS5493950 A JP S5493950A JP 76778 A JP76778 A JP 76778A JP 76778 A JP76778 A JP 76778A JP S5493950 A JPS5493950 A JP S5493950A
Authority
JP
Japan
Prior art keywords
pulse
voltage
width
time
switch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP76778A
Other languages
Japanese (ja)
Inventor
Katsuharu Asai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP76778A priority Critical patent/JPS5493950A/en
Publication of JPS5493950A publication Critical patent/JPS5493950A/en
Pending legal-status Critical Current

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  • Manipulation Of Pulses (AREA)

Abstract

PURPOSE: To obtain a pulse amplifier circuit which can amplify and control the output of a pulse generator by using no active elements.
CONSTITUTION: The output of pulse generator 1 enters switch 2, and pulses enter a delay circuit through switch SW. Switches SW1 to SWn are operated only during prescribed times respectively. In case of n=4, the pulse with pulse width 4td and voltage v enters switch 2. In switch 2, since SW4 is closed only during time td, the pulse with width td enters delay circuit 5 of delay time 3td and reaches pulse transformer 3 after time 3td. SW3 is closed during time td simultaneously SW4 opening. Thus, since switches are operated correspondingly to the delay time of delay circuit 5, outputs from respective circuits of the input signal appear in pulse transformer 3 as the pulse with width dt and voltage v at the same time. As a result, the pulse with width td and voltage 4v appears in load 4, and the voltage is amplified by a factor 4.
COPYRIGHT: (C)1979,JPO&Japio
JP76778A 1978-01-06 1978-01-06 Pulse amplifier circuit Pending JPS5493950A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP76778A JPS5493950A (en) 1978-01-06 1978-01-06 Pulse amplifier circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP76778A JPS5493950A (en) 1978-01-06 1978-01-06 Pulse amplifier circuit

Publications (1)

Publication Number Publication Date
JPS5493950A true JPS5493950A (en) 1979-07-25

Family

ID=11482838

Family Applications (1)

Application Number Title Priority Date Filing Date
JP76778A Pending JPS5493950A (en) 1978-01-06 1978-01-06 Pulse amplifier circuit

Country Status (1)

Country Link
JP (1) JPS5493950A (en)

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