JPS5487423A - Tow-dimentional hadamardsigma transformation system - Google Patents

Tow-dimentional hadamardsigma transformation system

Info

Publication number
JPS5487423A
JPS5487423A JP15593377A JP15593377A JPS5487423A JP S5487423 A JPS5487423 A JP S5487423A JP 15593377 A JP15593377 A JP 15593377A JP 15593377 A JP15593377 A JP 15593377A JP S5487423 A JPS5487423 A JP S5487423A
Authority
JP
Japan
Prior art keywords
screen memory
matrix
stored
hadamard
dimentional
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15593377A
Other languages
Japanese (ja)
Inventor
Takeyasu Morigami
Satoyuki Cho
Yoshikatsu Matsui
Eiji Yonemoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP15593377A priority Critical patent/JPS5487423A/en
Publication of JPS5487423A publication Critical patent/JPS5487423A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To perform a transformation process at a high speed by providing a two- dimentional hadamard's transformation method for pictures.
CONSTITUTION: An original picture, regarded as matrix [A] of N rows by N columns, is stored in the 1st screen memory FM2. Then, N-order Hadamard's matrix [H] of N rows by N columns is stored in the 2nd screen memory FM3. According to Hadamard's matrix [H] in screen memory FM3, original picture [A] in screen memory FM2 is integrated by arithmetic circuit ALU and transformation picture [B] is stored in screen memory FM1. Next, transposed matrix [Bt] is obtained with read-out address of screen memory FM1 made inverse to write addresses and integrated, according to Hadamard's matrix [H], by arithmetic circuit ALU to obtain a transform picture, which is stored in screen memory FM2 . Contents of screen memories FM1 to FM3 can be displayed on cathode-ray tibe by being selected by alternation switch S.
COPYRIGHT: (C)1979,JPO&Japio
JP15593377A 1977-12-23 1977-12-23 Tow-dimentional hadamardsigma transformation system Pending JPS5487423A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15593377A JPS5487423A (en) 1977-12-23 1977-12-23 Tow-dimentional hadamardsigma transformation system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15593377A JPS5487423A (en) 1977-12-23 1977-12-23 Tow-dimentional hadamardsigma transformation system

Publications (1)

Publication Number Publication Date
JPS5487423A true JPS5487423A (en) 1979-07-11

Family

ID=15616678

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15593377A Pending JPS5487423A (en) 1977-12-23 1977-12-23 Tow-dimentional hadamardsigma transformation system

Country Status (1)

Country Link
JP (1) JPS5487423A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5644517A (en) * 1992-10-22 1997-07-01 International Business Machines Corporation Method for performing matrix transposition on a mesh multiprocessor architecture having multiple processor with concurrent execution of the multiple processors

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5644517A (en) * 1992-10-22 1997-07-01 International Business Machines Corporation Method for performing matrix transposition on a mesh multiprocessor architecture having multiple processor with concurrent execution of the multiple processors

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