JPS5487424A - Linear hadamardsigma transformation system - Google Patents

Linear hadamardsigma transformation system

Info

Publication number
JPS5487424A
JPS5487424A JP15593477A JP15593477A JPS5487424A JP S5487424 A JPS5487424 A JP S5487424A JP 15593477 A JP15593477 A JP 15593477A JP 15593477 A JP15593477 A JP 15593477A JP S5487424 A JPS5487424 A JP S5487424A
Authority
JP
Japan
Prior art keywords
screen
screen memory
hadamard
data
read out
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15593477A
Other languages
Japanese (ja)
Inventor
Takeyasu Morigami
Satoyuki Cho
Yoshikatsu Matsui
Eiji Yonemoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP15593477A priority Critical patent/JPS5487424A/en
Publication of JPS5487424A publication Critical patent/JPS5487424A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To perform a transformation process at a high speed by providing a linear hadamard's tranformation method for pictures.
CONSTITUTION: Through the control of controller CONT, data for the entire screen acreen are read out from FM1 and applied to arithmetic circuit ALU. While data for the entire screen are read out once from screen memory FM1, data for one line of a Hadamard's matrix are read out repeatedly from screen memory FM2 and applied to arithmetic circuit ALU. In arithmetic circuit ALU, an original picture from screen memory FM1 is integrated for one line by being added or subtracted according to the contents of the Hadamard's matrix, and the results are set from read- back circuit RBC into screen memory FM3 by way of common bus BS. The same operation is done until the N-th row of the original picture to obtain a transformation picture, which is set into screen memory FM3. The contents of screen memries FM1 to FM3 can be displayed on CRT.
COPYRIGHT: (C)1979,JPO&Japio
JP15593477A 1977-12-23 1977-12-23 Linear hadamardsigma transformation system Pending JPS5487424A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15593477A JPS5487424A (en) 1977-12-23 1977-12-23 Linear hadamardsigma transformation system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15593477A JPS5487424A (en) 1977-12-23 1977-12-23 Linear hadamardsigma transformation system

Publications (1)

Publication Number Publication Date
JPS5487424A true JPS5487424A (en) 1979-07-11

Family

ID=15616698

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15593477A Pending JPS5487424A (en) 1977-12-23 1977-12-23 Linear hadamardsigma transformation system

Country Status (1)

Country Link
JP (1) JPS5487424A (en)

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