JPS5481059A - Analog signal output equipment - Google Patents

Analog signal output equipment

Info

Publication number
JPS5481059A
JPS5481059A JP14901677A JP14901677A JPS5481059A JP S5481059 A JPS5481059 A JP S5481059A JP 14901677 A JP14901677 A JP 14901677A JP 14901677 A JP14901677 A JP 14901677A JP S5481059 A JPS5481059 A JP S5481059A
Authority
JP
Japan
Prior art keywords
time
voltage
switching element
holding circuit
analog signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14901677A
Other languages
Japanese (ja)
Inventor
Kuniyoshi Konishi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP14901677A priority Critical patent/JPS5481059A/en
Publication of JPS5481059A publication Critical patent/JPS5481059A/en
Pending legal-status Critical Current

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  • Analogue/Digital Conversion (AREA)

Abstract

PURPOSE: To obtain a high-precision analog signal equivalent to even high-speed data, by equipping a sample holding circuit which inhibits the inputting of an output analog voltage within a fixed period at the switching time of signals of the input digital amount.
CONSTITUTION: Data DATA supplied to digital-to-analog converter D/A-C101 are converted into current value I depending upon the contents, and by OP-A1102 and resistance R, it is converted into a voltage value, which is accumulated in holding capacitor CH via switching element SW of sample holding circuit 103 before being transmitted to booster 104. With input data switched, a grid voltage is outputted at that time from OP-A1. In holding circuit 103, however, switching element SW is previously controlled to turn OFF with margin time T1 and, in consequence, no grid voltage is inputted. In this way, switching element SW is controlled to turn ON again after time T2, thereby outputting an analog voltage after the switching.
COPYRIGHT: (C)1979,JPO&Japio
JP14901677A 1977-12-12 1977-12-12 Analog signal output equipment Pending JPS5481059A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14901677A JPS5481059A (en) 1977-12-12 1977-12-12 Analog signal output equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14901677A JPS5481059A (en) 1977-12-12 1977-12-12 Analog signal output equipment

Publications (1)

Publication Number Publication Date
JPS5481059A true JPS5481059A (en) 1979-06-28

Family

ID=15465821

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14901677A Pending JPS5481059A (en) 1977-12-12 1977-12-12 Analog signal output equipment

Country Status (1)

Country Link
JP (1) JPS5481059A (en)

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