JPS5478012A - Clamp circuit - Google Patents

Clamp circuit

Info

Publication number
JPS5478012A
JPS5478012A JP14557177A JP14557177A JPS5478012A JP S5478012 A JPS5478012 A JP S5478012A JP 14557177 A JP14557177 A JP 14557177A JP 14557177 A JP14557177 A JP 14557177A JP S5478012 A JPS5478012 A JP S5478012A
Authority
JP
Japan
Prior art keywords
signals
input
switch circuit
input signals
capacitor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14557177A
Other languages
Japanese (ja)
Inventor
Isao Tashiro
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP14557177A priority Critical patent/JPS5478012A/en
Publication of JPS5478012A publication Critical patent/JPS5478012A/en
Pending legal-status Critical Current

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  • Picture Signal Circuits (AREA)

Abstract

PURPOSE: To eliminate effectively synchronizing signals without giving distortion to an output waveform, by providing a switch circuit in the input side of a buffer amplifier for TV signals.
CONSTITUTION: Input signals are inputted to high-input impedance buffer amplifier 13 through switch circuit 11 using a FET element and capacitor 12. The input of amplifier 13 is grounded through switch circuit 14 using a FET element, and the turning-on and off of switches 11 and 14 is controlled by control circuit 15 which is operated at the timing of synchronizing signals of input signals. As a result, the synchronizing signal field is stopped by switch 11 to accumulate the difference between the ground level and the pedestal level of input signals in capacitor 12, and input signals are accurately clamped at the pedestal level.
COPYRIGHT: (C)1979,JPO&Japio
JP14557177A 1977-12-03 1977-12-03 Clamp circuit Pending JPS5478012A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14557177A JPS5478012A (en) 1977-12-03 1977-12-03 Clamp circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14557177A JPS5478012A (en) 1977-12-03 1977-12-03 Clamp circuit

Publications (1)

Publication Number Publication Date
JPS5478012A true JPS5478012A (en) 1979-06-21

Family

ID=15388184

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14557177A Pending JPS5478012A (en) 1977-12-03 1977-12-03 Clamp circuit

Country Status (1)

Country Link
JP (1) JPS5478012A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6285577A (en) * 1985-10-01 1987-04-20 アールシーエー　トムソン　ライセンシング　コーポレイシヨン Wide band video signal processor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6285577A (en) * 1985-10-01 1987-04-20 アールシーエー　トムソン　ライセンシング　コーポレイシヨン Wide band video signal processor

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