JPS5472618A - Control system for picture signal sending - Google Patents

Control system for picture signal sending

Info

Publication number
JPS5472618A
JPS5472618A JP13966377A JP13966377A JPS5472618A JP S5472618 A JPS5472618 A JP S5472618A JP 13966377 A JP13966377 A JP 13966377A JP 13966377 A JP13966377 A JP 13966377A JP S5472618 A JPS5472618 A JP S5472618A
Authority
JP
Japan
Prior art keywords
memory
read
signal
signals
picture
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13966377A
Other languages
Japanese (ja)
Inventor
Kyoji Koseki
Takuo Fudanotsuji
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Nippon Telegraph and Telephone Corp
Original Assignee
Fujitsu Ltd
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Nippon Telegraph and Telephone Corp filed Critical Fujitsu Ltd
Priority to JP13966377A priority Critical patent/JPS5472618A/en
Publication of JPS5472618A publication Critical patent/JPS5472618A/en
Pending legal-status Critical Current

Links

Landscapes

  • Facsimile Scanning Arrangements (AREA)
  • Storing Facsimile Image Data (AREA)

Abstract

PURPOSE: To enable to transmit correct signals efficiently by storing and correcting picture signals to one memory while picture signals are read from other memory.
CONSTITUTION: A read signal applied from read element CCD and a control signal outputted from write counter WCT are supplied to memory MEML through SW1 as write signals LW and write read data RD in memory MEML under control of counter WCT. Then, switches SW1 and SW2 are exchanged according to the sending speed of transmitting signal SD. When switch SW2 is set to the MEML side and SW1 is set to the MEMR side, read signal RD is entered and stored in memory MEMR. Thus, while a picture signal is read from one memory, the picture signal is stored and corrected in another memory, the picture signal is stored and corrected in another memory, so that correct signals can be transmitted efficiently.
COPYRIGHT: (C)1979,JPO&Japio
JP13966377A 1977-11-21 1977-11-21 Control system for picture signal sending Pending JPS5472618A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13966377A JPS5472618A (en) 1977-11-21 1977-11-21 Control system for picture signal sending

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13966377A JPS5472618A (en) 1977-11-21 1977-11-21 Control system for picture signal sending

Publications (1)

Publication Number Publication Date
JPS5472618A true JPS5472618A (en) 1979-06-11

Family

ID=15250510

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13966377A Pending JPS5472618A (en) 1977-11-21 1977-11-21 Control system for picture signal sending

Country Status (1)

Country Link
JP (1) JPS5472618A (en)

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