JPS5463660A - Fm demodulator circuit - Google Patents

Fm demodulator circuit

Info

Publication number
JPS5463660A
JPS5463660A JP12961977A JP12961977A JPS5463660A JP S5463660 A JPS5463660 A JP S5463660A JP 12961977 A JP12961977 A JP 12961977A JP 12961977 A JP12961977 A JP 12961977A JP S5463660 A JPS5463660 A JP S5463660A
Authority
JP
Japan
Prior art keywords
voltage
amplifier
limiting amplifier
detector
input terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12961977A
Other languages
Japanese (ja)
Inventor
Kazuo Ikeda
Hiroshi Fukushima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP12961977A priority Critical patent/JPS5463660A/en
Publication of JPS5463660A publication Critical patent/JPS5463660A/en
Pending legal-status Critical Current

Links

Landscapes

  • Circuits Of Receivers In General (AREA)
  • Noise Elimination (AREA)

Abstract

PURPOSE: To operate normally a signal meter and a muting circuit, which are operated by the output voltage of a level detector, by preventing the level detector from detecting levels erroneously due to the oscillation voltage of a voltage control oscillator.
CONSTITUTION: A limiting amplifier at the last stage of a multi-stage FMIF limiting amplifier is divided into the first limiting amplifier 4 and the second limiting amplifier 15 which have only the input terminal connected in parallel, and the output terminal of amplifier 4 is connected to the input terminal of phase comparator 7, thereby cnstituting a PLL system FM demodulator circuit. Meanwhile, the output terminal of amplifier 15 is connected to level detector 13 which is provided for tak- ing out the signal meter driving voltage and the muting control voltage. As a result, detector 13 is not affected by the oscillation voltage of voltage control oscillator 10 which is injected to input terminal 6 of comparator 7, so that the erroneous detection of detector 13 can be prevented.
COPYRIGHT: (C)1979,JPO&Japio
JP12961977A 1977-10-31 1977-10-31 Fm demodulator circuit Pending JPS5463660A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12961977A JPS5463660A (en) 1977-10-31 1977-10-31 Fm demodulator circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12961977A JPS5463660A (en) 1977-10-31 1977-10-31 Fm demodulator circuit

Publications (1)

Publication Number Publication Date
JPS5463660A true JPS5463660A (en) 1979-05-22

Family

ID=15013939

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12961977A Pending JPS5463660A (en) 1977-10-31 1977-10-31 Fm demodulator circuit

Country Status (1)

Country Link
JP (1) JPS5463660A (en)

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