JPS54148457A - Integral analog input device - Google Patents

Integral analog input device

Info

Publication number
JPS54148457A
JPS54148457A JP5659178A JP5659178A JPS54148457A JP S54148457 A JPS54148457 A JP S54148457A JP 5659178 A JP5659178 A JP 5659178A JP 5659178 A JP5659178 A JP 5659178A JP S54148457 A JPS54148457 A JP S54148457A
Authority
JP
Japan
Prior art keywords
noise
frequency
control
integrating
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5659178A
Other languages
Japanese (ja)
Inventor
Kazuhiko Shimoyama
Takayoshi Kitada
Yukiyoshi Kato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP5659178A priority Critical patent/JPS54148457A/en
Publication of JPS54148457A publication Critical patent/JPS54148457A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To eliminate the extenal noise when the analog signals are integrated and thus to reduce the error by varying the oscillation frequency which determines the sampling and integrating cycles.
CONSTITUTION: The internal control signals are produced by using external AC input 6 (such as commerical frequency) given from the subject system as the fundamental frequency. The zero point of input 6 is detected through zero-point detection circuit 10 to deliver basic clock 23. Receiving this output, divider circuit delivers division signal 13 which is necessary for the internal operation. Control circuit 18 performs the counting action for signal 13 and delivers a series of control signal 8 to control the integrating action, writing into register 4 and others. In this way, both the sampling and integrating cycles can be varied in accordance with the frequency variation of the subject system. Thus, the external noise can be eliminated, reducing the error caused by the noise.
COPYRIGHT: (C)1979,JPO&Japio
JP5659178A 1978-05-15 1978-05-15 Integral analog input device Pending JPS54148457A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5659178A JPS54148457A (en) 1978-05-15 1978-05-15 Integral analog input device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5659178A JPS54148457A (en) 1978-05-15 1978-05-15 Integral analog input device

Publications (1)

Publication Number Publication Date
JPS54148457A true JPS54148457A (en) 1979-11-20

Family

ID=13031424

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5659178A Pending JPS54148457A (en) 1978-05-15 1978-05-15 Integral analog input device

Country Status (1)

Country Link
JP (1) JPS54148457A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5943436A (en) * 1982-09-01 1984-03-10 Chino Works Ltd Input circuit
JPS6387573U (en) * 1986-11-27 1988-06-07

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5943436A (en) * 1982-09-01 1984-03-10 Chino Works Ltd Input circuit
JPS6322330B2 (en) * 1982-09-01 1988-05-11 Chino Corp
JPS6387573U (en) * 1986-11-27 1988-06-07

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