JPS5461424A - Reader - Google Patents

Reader

Info

Publication number
JPS5461424A
JPS5461424A JP12757777A JP12757777A JPS5461424A JP S5461424 A JPS5461424 A JP S5461424A JP 12757777 A JP12757777 A JP 12757777A JP 12757777 A JP12757777 A JP 12757777A JP S5461424 A JPS5461424 A JP S5461424A
Authority
JP
Japan
Prior art keywords
terminal
resistor
input
amplifier
fet
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12757777A
Other languages
Japanese (ja)
Inventor
Hidenori Yamamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP12757777A priority Critical patent/JPS5461424A/en
Publication of JPS5461424A publication Critical patent/JPS5461424A/en
Pending legal-status Critical Current

Links

Landscapes

  • Facsimile Image Signal Circuits (AREA)
  • Character Input (AREA)

Abstract

PURPOSE: To establish the reader simple in the circuit constitution, which can keep the scanning time constant independing of the size of paper, can detect the white level of paper, and can read-in the timing mark.
CONSTITUTION: The output end of the scanning section A is connected to the non- inverting input end of the operational amplifier 5 via the diode 3 and the resistor 4, the input terminal is grounded via the resistor 6, and is connected to the source of FET 8 through the capacitor 7. The drain of FET 8 is grounded and the gate is connected to the input terminal T1 through the resistor 9. Input signal (Fig.A) is fed to the terminal T1. Further, when the input signal is fed to the terminal T1, FET 8 is turned on only for the time T. The output terminal of the amplifier 5 and the inverting input are shortened, the output terminal of the amplifier 5 is grounded via the variable resistor 10 and the resistor 11, and the slider of the resistor 10 is connected to the non-inverting terminal of the comparator 12. The comparator 12 is connected to the output terminal T2, the non-inverting input terminal is connected to the output terminal of the amplifier 2, the junction between the resistors 10 and 11 is connected to the input terminal T3 via the resistor 13 and input signal (Fig. B) is fed to the terminal
COPYRIGHT: (C)1979,JPO&Japio
JP12757777A 1977-10-26 1977-10-26 Reader Pending JPS5461424A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12757777A JPS5461424A (en) 1977-10-26 1977-10-26 Reader

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12757777A JPS5461424A (en) 1977-10-26 1977-10-26 Reader

Publications (1)

Publication Number Publication Date
JPS5461424A true JPS5461424A (en) 1979-05-17

Family

ID=14963489

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12757777A Pending JPS5461424A (en) 1977-10-26 1977-10-26 Reader

Country Status (1)

Country Link
JP (1) JPS5461424A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57159175A (en) * 1981-03-25 1982-10-01 Fujitsu Ltd Picture signal quantizing ciruit
JPS5810962A (en) * 1981-07-14 1983-01-21 Victor Co Of Japan Ltd Binary coding circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57159175A (en) * 1981-03-25 1982-10-01 Fujitsu Ltd Picture signal quantizing ciruit
JPS5810962A (en) * 1981-07-14 1983-01-21 Victor Co Of Japan Ltd Binary coding circuit

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