JPS5458359A - Package and semiconductor device providing it - Google Patents

Package and semiconductor device providing it

Info

Publication number
JPS5458359A
JPS5458359A JP12452077A JP12452077A JPS5458359A JP S5458359 A JPS5458359 A JP S5458359A JP 12452077 A JP12452077 A JP 12452077A JP 12452077 A JP12452077 A JP 12452077A JP S5458359 A JPS5458359 A JP S5458359A
Authority
JP
Japan
Prior art keywords
silicon
package
increase
wiring
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12452077A
Other languages
Japanese (ja)
Inventor
Kanji Otsuka
Tamotsu Usami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP12452077A priority Critical patent/JPS5458359A/en
Publication of JPS5458359A publication Critical patent/JPS5458359A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PURPOSE:To increase thermal dissipation and to increase the mounting density, by making air-tight sealing for the semiconductor element having PN junction, in the package using silicon as the package material and taking the silicon as the base. CONSTITUTION:On the package 2 consisting of silicon, Au-Si eutectic alloy layer 3 is passed thru the LSI chip 1, and the insulation film 4 of silicon oxide or silicon nitride is coated on the main body 2 by surrounding it. Next, on the film 4, the conductive wiring 5 is made and bonding is made by using the chip 1 and the gold fine wire 6, and the wiring 5 is bonded with the external lead terminal 7 with solder 8. After that, the fixing material 10 is used for the upper part such as low melting point glass, and similarly, the package cover 9 of silicon is covered and air tight seal is made. Thus, the silicon excellent by 5 times for the thermal conductivity in comparsion with aluminum convertionally used is used and the heat dissipation can be increased.
JP12452077A 1977-10-19 1977-10-19 Package and semiconductor device providing it Pending JPS5458359A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12452077A JPS5458359A (en) 1977-10-19 1977-10-19 Package and semiconductor device providing it

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12452077A JPS5458359A (en) 1977-10-19 1977-10-19 Package and semiconductor device providing it

Publications (1)

Publication Number Publication Date
JPS5458359A true JPS5458359A (en) 1979-05-11

Family

ID=14887505

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12452077A Pending JPS5458359A (en) 1977-10-19 1977-10-19 Package and semiconductor device providing it

Country Status (1)

Country Link
JP (1) JPS5458359A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62248242A (en) * 1986-04-22 1987-10-29 Matsushita Electronics Corp Semiconductor device
US4905075A (en) * 1986-05-05 1990-02-27 General Electric Company Hermetic semiconductor enclosure

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3517278A (en) * 1967-10-02 1970-06-23 Teledyne Inc Flip chip structure

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3517278A (en) * 1967-10-02 1970-06-23 Teledyne Inc Flip chip structure

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62248242A (en) * 1986-04-22 1987-10-29 Matsushita Electronics Corp Semiconductor device
US4905075A (en) * 1986-05-05 1990-02-27 General Electric Company Hermetic semiconductor enclosure

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