JPS5455148A - Automatic equalizer - Google Patents
Automatic equalizerInfo
- Publication number
- JPS5455148A JPS5455148A JP12138777A JP12138777A JPS5455148A JP S5455148 A JPS5455148 A JP S5455148A JP 12138777 A JP12138777 A JP 12138777A JP 12138777 A JP12138777 A JP 12138777A JP S5455148 A JPS5455148 A JP S5455148A
- Authority
- JP
- Japan
- Prior art keywords
- outputs
- signal
- multiplier
- stage
- terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03006—Arrangements for removing intersymbol interference
- H04L25/03012—Arrangements for removing intersymbol interference operating in the time domain
- H04L25/03019—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception
- H04L25/03038—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception with a non-recursive structure
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Filters That Use Time-Delay Elements (AREA)
- Dc Digital Transmission (AREA)
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
Abstract
PURPOSE:To correct automatically correct distortion generated on a transmission line at a reception side, by composing the device of a method which sums products between delay outputs and sampled values. CONSTITUTION:Shift register 2 has past reception signal (r) stored in i-th stage 2-i. Memory 3, on the other hand, has impulse signal (h) stored in i-th stage 3-i. Multiplier 4 outputs the product between values (r) and (h) of 2-i and 3-i. Further, adder 5 outputs the sum of outputs of the multiplier to terminal 6. Then, the signal of terminal 6 realizes convolutional integration approximately and reception signals (r) and (t) can be obtained here which have been corrected.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12138777A JPS5455148A (en) | 1977-10-12 | 1977-10-12 | Automatic equalizer |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12138777A JPS5455148A (en) | 1977-10-12 | 1977-10-12 | Automatic equalizer |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5455148A true JPS5455148A (en) | 1979-05-02 |
Family
ID=14809932
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP12138777A Pending JPS5455148A (en) | 1977-10-12 | 1977-10-12 | Automatic equalizer |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5455148A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5850812A (en) * | 1981-09-21 | 1983-03-25 | Matsushita Electric Ind Co Ltd | Transmitting circuit for audio signal |
-
1977
- 1977-10-12 JP JP12138777A patent/JPS5455148A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5850812A (en) * | 1981-09-21 | 1983-03-25 | Matsushita Electric Ind Co Ltd | Transmitting circuit for audio signal |
JPH0252886B2 (en) * | 1981-09-21 | 1990-11-15 | Matsushita Electric Ind Co Ltd |
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