JPS56169441A - Phase information extracting circuit - Google Patents
Phase information extracting circuitInfo
- Publication number
- JPS56169441A JPS56169441A JP7340480A JP7340480A JPS56169441A JP S56169441 A JPS56169441 A JP S56169441A JP 7340480 A JP7340480 A JP 7340480A JP 7340480 A JP7340480 A JP 7340480A JP S56169441 A JPS56169441 A JP S56169441A
- Authority
- JP
- Japan
- Prior art keywords
- taps
- delay line
- phase information
- information extracting
- extracting circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B3/00—Line transmission systems
- H04B3/02—Details
- H04B3/04—Control of transmission; Equalising
- H04B3/14—Control of transmission; Equalising characterised by the equalising network used
- H04B3/146—Control of transmission; Equalising characterised by the equalising network used using phase-frequency equalisers
- H04B3/148—Control of transmission; Equalising characterised by the equalising network used using phase-frequency equalisers variable equalisers
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Filters That Use Time-Delay Elements (AREA)
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
Abstract
PURPOSE:To erase or attenuate echos, by providing a preequalizer at the prestage of a transversal type automatic equalizer. CONSTITUTION:An input signal from an IN terminal is given to a delay line 13 having taps every pulse time interval T0 and it is picked up from each tap to an adder 15 via a weighting circuit. Further, by adjusting each tap weighting circuit suitably, the echo produced at taps of the delay line 3 due to a group delay distortion can be attenuated. In the figure, the prequalizer EQ is shown as 1, a VSB demodulator DEM as 2 and the delay line with taps as phi, respectively.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7340480A JPS56169441A (en) | 1980-05-30 | 1980-05-30 | Phase information extracting circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7340480A JPS56169441A (en) | 1980-05-30 | 1980-05-30 | Phase information extracting circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS56169441A true JPS56169441A (en) | 1981-12-26 |
JPS645771B2 JPS645771B2 (en) | 1989-01-31 |
Family
ID=13517217
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7340480A Granted JPS56169441A (en) | 1980-05-30 | 1980-05-30 | Phase information extracting circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56169441A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59182636A (en) * | 1983-03-31 | 1984-10-17 | Fujitsu Ltd | Data mode drawing system |
-
1980
- 1980-05-30 JP JP7340480A patent/JPS56169441A/en active Granted
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59182636A (en) * | 1983-03-31 | 1984-10-17 | Fujitsu Ltd | Data mode drawing system |
Also Published As
Publication number | Publication date |
---|---|
JPS645771B2 (en) | 1989-01-31 |
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