JPS5446476A - Integrated-circuit package - Google Patents

Integrated-circuit package

Info

Publication number
JPS5446476A
JPS5446476A JP11309977A JP11309977A JPS5446476A JP S5446476 A JPS5446476 A JP S5446476A JP 11309977 A JP11309977 A JP 11309977A JP 11309977 A JP11309977 A JP 11309977A JP S5446476 A JPS5446476 A JP S5446476A
Authority
JP
Japan
Prior art keywords
terminal
normal
scan
scan path
tests
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11309977A
Other languages
Japanese (ja)
Inventor
Masato Kawai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP11309977A priority Critical patent/JPS5446476A/en
Publication of JPS5446476A publication Critical patent/JPS5446476A/en
Pending legal-status Critical Current

Links

Landscapes

  • Tests Of Electronic Circuits (AREA)

Abstract

PURPOSE: To give interchangeability with a package without a scan path, and to make tests possible by using the scan path by providing a scan-path terminal to a side independent of a normal terminal, top surface or reverse surface.
CONSTITUTION: As for mounting, only normal input-output terminal 2 is used so as to maintain interchangeability with the same kind of a package as conventional one, and as to tests, terminal 3 is used for tests by the scan path. In a test time, terminal 3 is taken as a shift mode setting terminal, and data is scanned in and out by using terminal 2. Since the shift mode is exclusive with a normal mode, one terminal can be given different functions in the shift mode and in the normal mode. Terminal 2 assigned to the scan-in data input-output terminal is connected to both the scan path with its memory element consituted in the shift register and the normal internal circuit
COPYRIGHT: (C)1979,JPO&Japio
JP11309977A 1977-09-19 1977-09-19 Integrated-circuit package Pending JPS5446476A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11309977A JPS5446476A (en) 1977-09-19 1977-09-19 Integrated-circuit package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11309977A JPS5446476A (en) 1977-09-19 1977-09-19 Integrated-circuit package

Publications (1)

Publication Number Publication Date
JPS5446476A true JPS5446476A (en) 1979-04-12

Family

ID=14603447

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11309977A Pending JPS5446476A (en) 1977-09-19 1977-09-19 Integrated-circuit package

Country Status (1)

Country Link
JP (1) JPS5446476A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6381268U (en) * 1986-11-17 1988-05-28

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6381268U (en) * 1986-11-17 1988-05-28

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