JPS5420315B2 - - Google Patents

Info

Publication number
JPS5420315B2
JPS5420315B2 JP8094974A JP8094974A JPS5420315B2 JP S5420315 B2 JPS5420315 B2 JP S5420315B2 JP 8094974 A JP8094974 A JP 8094974A JP 8094974 A JP8094974 A JP 8094974A JP S5420315 B2 JPS5420315 B2 JP S5420315B2
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP8094974A
Other languages
Japanese (ja)
Other versions
JPS519681A (https=
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP8094974A priority Critical patent/JPS5420315B2/ja
Publication of JPS519681A publication Critical patent/JPS519681A/ja
Publication of JPS5420315B2 publication Critical patent/JPS5420315B2/ja
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/075Connecting or disconnecting of bond wires
    • H10W72/07551Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
    • H10W72/07554Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting changes in dispositions
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/541Dispositions of bond wires
    • H10W72/5449Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/541Dispositions of bond wires
    • H10W72/547Dispositions of multiple bond wires
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/90Bond pads, in general
    • H10W72/931Shapes of bond pads
    • H10W72/932Plan-view shape, i.e. in top view
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Wire Bonding (AREA)
JP8094974A 1974-07-15 1974-07-15 Expired JPS5420315B2 (https=)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8094974A JPS5420315B2 (https=) 1974-07-15 1974-07-15

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8094974A JPS5420315B2 (https=) 1974-07-15 1974-07-15

Publications (2)

Publication Number Publication Date
JPS519681A JPS519681A (https=) 1976-01-26
JPS5420315B2 true JPS5420315B2 (https=) 1979-07-21

Family

ID=13732738

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8094974A Expired JPS5420315B2 (https=) 1974-07-15 1974-07-15

Country Status (1)

Country Link
JP (1) JPS5420315B2 (https=)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5746600Y2 (https=) * 1977-01-31 1982-10-14
JPS5651851A (en) * 1979-10-05 1981-05-09 Hitachi Ltd Semiconductor device
JPS58127338A (ja) * 1982-01-25 1983-07-29 Sharp Corp 電子部品の構造
JPS60143639A (ja) * 1983-12-29 1985-07-29 Konishiroku Photo Ind Co Ltd 集積回路装置

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
ELECTRONIC DESIGN=1967 *

Also Published As

Publication number Publication date
JPS519681A (https=) 1976-01-26

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