JPS5419677A - Method of producing semiconductor - Google Patents
Method of producing semiconductorInfo
- Publication number
- JPS5419677A JPS5419677A JP7662378A JP7662378A JPS5419677A JP S5419677 A JPS5419677 A JP S5419677A JP 7662378 A JP7662378 A JP 7662378A JP 7662378 A JP7662378 A JP 7662378A JP S5419677 A JPS5419677 A JP S5419677A
- Authority
- JP
- Japan
- Prior art keywords
- producing semiconductor
- semiconductor
- producing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H10P14/69433—
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0112—Integrating together multiple components covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating multiple BJTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
-
- H10P14/662—
-
- H10P14/69215—
-
- H10P14/6927—
-
- H10P76/40—
-
- H10P14/6329—
-
- H10P14/6334—
Landscapes
- Engineering & Computer Science (AREA)
- Bipolar Transistors (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US05/814,829 US4131497A (en) | 1977-07-12 | 1977-07-12 | Method of manufacturing self-aligned semiconductor devices |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5419677A true JPS5419677A (en) | 1979-02-14 |
| JPS6138623B2 JPS6138623B2 (enExample) | 1986-08-30 |
Family
ID=25216103
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7662378A Granted JPS5419677A (en) | 1977-07-12 | 1978-06-26 | Method of producing semiconductor |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US4131497A (enExample) |
| EP (1) | EP0000326B1 (enExample) |
| JP (1) | JPS5419677A (enExample) |
| DE (1) | DE2860161D1 (enExample) |
Families Citing this family (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4210689A (en) * | 1977-12-26 | 1980-07-01 | Tokyo Shibaura Denki Kabushiki Kaisha | Method of producing semiconductor devices |
| US4263057A (en) * | 1978-04-19 | 1981-04-21 | Rca Corporation | Method of manufacturing short channel MOS devices |
| US4199380A (en) * | 1978-11-13 | 1980-04-22 | Motorola, Inc. | Integrated circuit method |
| FR2454698A1 (fr) * | 1979-04-20 | 1980-11-14 | Radiotechnique Compelec | Procede de realisation de circuits integres a l'aide d'un masque multicouche et dispositifs obtenus par ce procede |
| US4243435A (en) * | 1979-06-22 | 1981-01-06 | International Business Machines Corporation | Bipolar transistor fabrication process with an ion implanted emitter |
| US4272882A (en) * | 1980-05-08 | 1981-06-16 | Rca Corporation | Method of laying out an integrated circuit with specific alignment of the collector contact with the emitter region |
| EP0054303B1 (en) * | 1980-12-17 | 1986-06-11 | Matsushita Electric Industrial Co., Ltd. | Semiconductor integrated circuit |
| US4436593A (en) | 1981-07-13 | 1984-03-13 | Memorex Corporation | Self-aligned pole tips |
| JPH0249280U (enExample) * | 1988-09-30 | 1990-04-05 | ||
| US5079177A (en) * | 1989-09-19 | 1992-01-07 | National Semiconductor Corporation | Process for fabricating high performance bicmos circuits |
| JP2509717B2 (ja) * | 1989-12-06 | 1996-06-26 | 株式会社東芝 | 半導体装置の製造方法 |
| US5702959A (en) * | 1995-05-31 | 1997-12-30 | Texas Instruments Incorporated | Method for making an isolated vertical transistor |
| KR102013416B1 (ko) * | 2012-10-26 | 2019-08-22 | 어플라이드 머티어리얼스, 인코포레이티드 | 조합 마스킹 |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50104872A (enExample) * | 1974-01-17 | 1975-08-19 | ||
| JPS5223263A (en) * | 1975-08-18 | 1977-02-22 | Nec Corp | Method of manufacturing semiconductor device |
Family Cites Families (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3967981A (en) * | 1971-01-14 | 1976-07-06 | Shumpei Yamazaki | Method for manufacturing a semiconductor field effort transistor |
| NL173110C (nl) * | 1971-03-17 | 1983-12-01 | Philips Nv | Werkwijze ter vervaardiging van een halfgeleiderinrichting, waarbij op een oppervlak van een halfgeleiderlichaam een uit ten minste twee deellagen van verschillend materiaal samengestelde maskeringslaag wordt aangebracht. |
| US4028150A (en) * | 1973-05-03 | 1977-06-07 | Ibm Corporation | Method for making reliable MOSFET device |
| US3900352A (en) * | 1973-11-01 | 1975-08-19 | Ibm | Isolated fixed and variable threshold field effect transistor fabrication technique |
| US3928082A (en) * | 1973-12-28 | 1975-12-23 | Texas Instruments Inc | Self-aligned transistor process |
| US3948694A (en) * | 1975-04-30 | 1976-04-06 | Motorola, Inc. | Self-aligned method for integrated circuit manufacture |
| US3961999A (en) * | 1975-06-30 | 1976-06-08 | Ibm Corporation | Method for forming recessed dielectric isolation with a minimized "bird's beak" problem |
| US4053349A (en) * | 1976-02-02 | 1977-10-11 | Intel Corporation | Method for forming a narrow gap |
| US4060427A (en) * | 1976-04-05 | 1977-11-29 | Ibm Corporation | Method of forming an integrated circuit region through the combination of ion implantation and diffusion steps |
| US4052229A (en) * | 1976-06-25 | 1977-10-04 | Intel Corporation | Process for preparing a substrate for mos devices of different thresholds |
| US4040891A (en) * | 1976-06-30 | 1977-08-09 | Ibm Corporation | Etching process utilizing the same positive photoresist layer for two etching steps |
| US4061530A (en) * | 1976-07-19 | 1977-12-06 | Fairchild Camera And Instrument Corporation | Process for producing successive stages of a charge coupled device |
-
1977
- 1977-07-12 US US05/814,829 patent/US4131497A/en not_active Expired - Lifetime
-
1978
- 1978-06-02 DE DE7878100081T patent/DE2860161D1/de not_active Expired
- 1978-06-02 EP EP78100081A patent/EP0000326B1/de not_active Expired
- 1978-06-26 JP JP7662378A patent/JPS5419677A/ja active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50104872A (enExample) * | 1974-01-17 | 1975-08-19 | ||
| JPS5223263A (en) * | 1975-08-18 | 1977-02-22 | Nec Corp | Method of manufacturing semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| EP0000326B1 (de) | 1980-09-17 |
| DE2860161D1 (en) | 1980-12-18 |
| EP0000326A1 (de) | 1979-01-24 |
| US4131497A (en) | 1978-12-26 |
| JPS6138623B2 (enExample) | 1986-08-30 |
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