Classifications

• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
  • G06F1/22—Means for limiting or controlling the pin/gate ratio
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
  • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
  • H03K19/0175—Coupling arrangements; Interface arrangements
  • H03K19/017545—Coupling arrangements; Impedance matching circuits
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
  • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
  • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
  • H03K19/1731—Optimisation thereof
  • H03K19/1732—Optimisation thereof by limitation or reduction of the pin/gate ratio
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/0001—Technical content checked by a classifier
  • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/30—Technical effects
  • H01L2924/301—Electrical effects
  • H01L2924/3011—Impedance

Landscapes

• Engineering & Computer Science (AREA)
• Computer Hardware Design (AREA)
• Physics & Mathematics (AREA)
• General Engineering & Computer Science (AREA)
• Theoretical Computer Science (AREA)
• Computing Systems (AREA)
• Mathematical Physics (AREA)
• General Physics & Mathematics (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• Power Engineering (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Semiconductor Integrated Circuits (AREA)
• Networks Using Active Elements (AREA)
• Processing Of Color Television Signals (AREA)
• Logic Circuits (AREA)

Applications Claiming Priority (1)

Publications (1)

Family

ID=6041189

Family Applications (1)

Country Status (4)

Families Citing this family (6)

Citations (1)

Family Cites Families (2)

• 1978
  • 1978-06-06 DE DE19782824862 patent/DE2824862A1/de active Granted
• 1979
  • 1979-05-29 FR FR7913590A patent/FR2428353A1/fr active Granted
  • 1979-06-05 GB GB7919512A patent/GB2023341B/en not_active Expired
  • 1979-06-06 JP JP7108679A patent/JPS54162438A/ja active Pending

Patent Citations (1)

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