JPS54158867A - Plasma etching unit - Google Patents

Plasma etching unit

Info

Publication number
JPS54158867A
JPS54158867A JP6800678A JP6800678A JPS54158867A JP S54158867 A JPS54158867 A JP S54158867A JP 6800678 A JP6800678 A JP 6800678A JP 6800678 A JP6800678 A JP 6800678A JP S54158867 A JPS54158867 A JP S54158867A
Authority
JP
Japan
Prior art keywords
pipe
reactor
circumference surface
etched
constitution
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6800678A
Other languages
Japanese (ja)
Inventor
Mitsuru Yamada
Yasuo Kinoshita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP6800678A priority Critical patent/JPS54158867A/en
Publication of JPS54158867A publication Critical patent/JPS54158867A/en
Pending legal-status Critical Current

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  • Drying Of Semiconductors (AREA)

Abstract

PURPOSE: To etch several objects under the uniform conditions by arranging a gas supply pipe and an exhaust pipe at an identical interval on the outer circumference surface and inner circumference surface of a reactor pipe formed in a doughnut shape and by forming two electrodes covering the reactor pipe.
CONSTITUTION: Reactor container 20 is formed of reactor pipe 2a which is formed of quartz in a horseshoe shape and contains etched object 1 inside, and pipe-shaped link lid 5a which links both the open parts of reactor pipe 2a together. Gas supply intake 3a and exhaust pipe 4a are arranged at an identical interval on the inner circumference surface and outer circumference surface of reactor container 20 respectively, and electrodes 7Aa and 7Bb for high-frequency power application are provided covering the upper half and lower half of reactor pipe 2a. In this constitution, several places identical in gas flow condition and in electric-field intensity are formed inside of reactor container 20, and consequently, etched objects 1 arranged there are etched under the even etching conditions, so that unevenness can be eliminated which occurs when several objects are etched simultaneously.
COPYRIGHT: (C)1979,JPO&Japio
JP6800678A 1978-06-05 1978-06-05 Plasma etching unit Pending JPS54158867A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6800678A JPS54158867A (en) 1978-06-05 1978-06-05 Plasma etching unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6800678A JPS54158867A (en) 1978-06-05 1978-06-05 Plasma etching unit

Publications (1)

Publication Number Publication Date
JPS54158867A true JPS54158867A (en) 1979-12-15

Family

ID=13361337

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6800678A Pending JPS54158867A (en) 1978-06-05 1978-06-05 Plasma etching unit

Country Status (1)

Country Link
JP (1) JPS54158867A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1986002289A1 (en) * 1984-10-19 1986-04-24 Tetron, Inc. Reactor apparatus for semiconductor wafer processing

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1986002289A1 (en) * 1984-10-19 1986-04-24 Tetron, Inc. Reactor apparatus for semiconductor wafer processing
JPS62500624A (en) * 1984-10-19 1987-03-12 テトロン・インコ−ポレ−テッド Reactor equipment for semiconductor wafer processing
US4694779A (en) * 1984-10-19 1987-09-22 Tetron, Inc. Reactor apparatus for semiconductor wafer processing

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