JPS54153675A - Frequency counter - Google Patents

Frequency counter

Info

Publication number
JPS54153675A
JPS54153675A JP6273178A JP6273178A JPS54153675A JP S54153675 A JPS54153675 A JP S54153675A JP 6273178 A JP6273178 A JP 6273178A JP 6273178 A JP6273178 A JP 6273178A JP S54153675 A JPS54153675 A JP S54153675A
Authority
JP
Japan
Prior art keywords
pulse
output
circuit
gate
input signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6273178A
Other languages
Japanese (ja)
Inventor
Hiroshi Shibata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP6273178A priority Critical patent/JPS54153675A/en
Publication of JPS54153675A publication Critical patent/JPS54153675A/en
Pending legal-status Critical Current

Links

Landscapes

  • Measuring Frequencies, Analyzing Spectra (AREA)

Abstract

PURPOSE: To enable accurate measurement results to be obtained at the minimum required latency time by automatically generating a reset pulse immediateby after an input signal is applied.
CONSTITUTION: An input signal is detected 3 after amplification 1 and when the output DC voltage thereof is larger than a reference voltage 4, the output of a comparator 5 changes, by which a monostable multi 6 is triggered. By the output pulse thereof, a gate control circuit 9 and a counter circuit 8 are reset. After the pulse from the monostable multi 6 erases, the circuit 9 immediately generates a gate pulse, by which a main gate 7 is opened, then the signals to be measured having passed through a waveform shaping circuit 2 are counted 8 and frequency display is accomplished.
COPYRIGHT: (C)1979,JPO&Japio
JP6273178A 1978-05-24 1978-05-24 Frequency counter Pending JPS54153675A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6273178A JPS54153675A (en) 1978-05-24 1978-05-24 Frequency counter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6273178A JPS54153675A (en) 1978-05-24 1978-05-24 Frequency counter

Publications (1)

Publication Number Publication Date
JPS54153675A true JPS54153675A (en) 1979-12-04

Family

ID=13208798

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6273178A Pending JPS54153675A (en) 1978-05-24 1978-05-24 Frequency counter

Country Status (1)

Country Link
JP (1) JPS54153675A (en)

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