JPS54152930A - Address decoder circuit - Google Patents

Address decoder circuit

Info

Publication number
JPS54152930A
JPS54152930A JP6110378A JP6110378A JPS54152930A JP S54152930 A JPS54152930 A JP S54152930A JP 6110378 A JP6110378 A JP 6110378A JP 6110378 A JP6110378 A JP 6110378A JP S54152930 A JPS54152930 A JP S54152930A
Authority
JP
Japan
Prior art keywords
level
signal
output
misfets
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6110378A
Other languages
Japanese (ja)
Other versions
JPS6043586B2 (en
Inventor
Shinji Nabeya
Toshibumi Inoue
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP53061103A priority Critical patent/JPS6043586B2/en
Publication of JPS54152930A publication Critical patent/JPS54152930A/en
Publication of JPS6043586B2 publication Critical patent/JPS6043586B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Static Random-Access Memory (AREA)

Abstract

PURPOSE:To reduce power consumption by preventing the output level from lowering by composing the address decoder circuit of a memory circuit of MISFETs and by turning OFF switching and load MISFETs with the chip unselected. CONSTITUTION:The logic block for an address decoder output is formed of MISFETs Q2 to Q4 and when operation control signal PD (chip selective signal) is held at level H, earth-side potential supply power switch MISFETQ5 and enhancement load MISFETQ6 of an inverter circuit are both turned ON. When address input signals (a1) to (an) are at level L, MISFETQ8 of the output circuit is ON and Q9 is OFF, so that a L-level selection signal will appear at terminal OUT. When even one of signals (a1) to (an) is at level H, a L-level unselective signal is outputted. With signal PD held at level L, FETs Q5 and Q6 both turn OFF and no direct current flows to the logic block, inverter circuits Q6 and Q7, and output circuits Q8 and Q9 having no relation with an input signal. Therefore, the power consumption with the chip unselected can be reduced greatly.
JP53061103A 1978-05-24 1978-05-24 Address decoder circuit Expired JPS6043586B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53061103A JPS6043586B2 (en) 1978-05-24 1978-05-24 Address decoder circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53061103A JPS6043586B2 (en) 1978-05-24 1978-05-24 Address decoder circuit

Publications (2)

Publication Number Publication Date
JPS54152930A true JPS54152930A (en) 1979-12-01
JPS6043586B2 JPS6043586B2 (en) 1985-09-28

Family

ID=13161406

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53061103A Expired JPS6043586B2 (en) 1978-05-24 1978-05-24 Address decoder circuit

Country Status (1)

Country Link
JP (1) JPS6043586B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4563598A (en) * 1981-12-28 1986-01-07 Fujitsu Limited Low power consuming decoder circuit for a semiconductor memory device
US4611131A (en) * 1983-08-31 1986-09-09 Texas Instruments Incorporated Low power decoder-driver circuit
JPS63127496A (en) * 1980-02-04 1988-05-31 テキサス　インスツルメンツ　インコ−ポレイテツド Low power consumption memory

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63104575U (en) * 1986-12-25 1988-07-06

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63127496A (en) * 1980-02-04 1988-05-31 テキサス　インスツルメンツ　インコ−ポレイテツド Low power consumption memory
JPH0234119B2 (en) * 1980-02-04 1990-08-01 Texas Instruments Inc
US4563598A (en) * 1981-12-28 1986-01-07 Fujitsu Limited Low power consuming decoder circuit for a semiconductor memory device
US4611131A (en) * 1983-08-31 1986-09-09 Texas Instruments Incorporated Low power decoder-driver circuit

Also Published As

Publication number Publication date
JPS6043586B2 (en) 1985-09-28

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