JPS54148428A - Phase converter circuit - Google Patents

Phase converter circuit

Info

Publication number
JPS54148428A
JPS54148428A JP5778378A JP5778378A JPS54148428A JP S54148428 A JPS54148428 A JP S54148428A JP 5778378 A JP5778378 A JP 5778378A JP 5778378 A JP5778378 A JP 5778378A JP S54148428 A JPS54148428 A JP S54148428A
Authority
JP
Japan
Prior art keywords
output
axis
input terminal
multiplexer
adder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5778378A
Other languages
Japanese (ja)
Other versions
JPS6148316B2 (en
Inventor
Kazuo Kashiki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP5778378A priority Critical patent/JPS54148428A/en
Publication of JPS54148428A publication Critical patent/JPS54148428A/en
Publication of JPS6148316B2 publication Critical patent/JPS6148316B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Color Television Systems (AREA)
  • Processing Of Color Television Signals (AREA)

Abstract

PURPOSE: To secure an easy conversion of ths subcarrier phase for the PAL signals by supplying the output of the 0-axis register directly to the multiplexer and the output of the 1- and 2-axis registers via the output of the interpolation circuit and the adder circuit respectively to be then drawn out to the 0-, 2- and 1-axis each.
CONSTITUTION: Output (b) of the 0-axis register 21 is applied to input terminal 27- 0 of multiplexer 27, and the output of 1-axis register 23 is applied to input terminal 27-2 of 27 through adder 28 after obtaining the output of the interpolation circuit. The output of the 2-axis register 24 is applied to input terminal 27-1 of 27 via adder 30 after obtaining the output of the interpolation circuit. Multiplexer 27 selects and delivers the signals of input terminal 27-0, 27-1 and 27-2 in that order, and thus the output features the sequence of the 0-, 2- and 1-axis in that order. As a result, the subcarrier phase of the PAL signals can be converted in a simple way.
COPYRIGHT: (C)1979,JPO&Japio
JP5778378A 1978-05-15 1978-05-15 Phase converter circuit Granted JPS54148428A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5778378A JPS54148428A (en) 1978-05-15 1978-05-15 Phase converter circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5778378A JPS54148428A (en) 1978-05-15 1978-05-15 Phase converter circuit

Publications (2)

Publication Number Publication Date
JPS54148428A true JPS54148428A (en) 1979-11-20
JPS6148316B2 JPS6148316B2 (en) 1986-10-23

Family

ID=13065465

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5778378A Granted JPS54148428A (en) 1978-05-15 1978-05-15 Phase converter circuit

Country Status (1)

Country Link
JP (1) JPS54148428A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6154786A (en) * 1984-08-27 1986-03-19 Nec Corp Forecasting coding device
JPS6156590A (en) * 1984-08-28 1986-03-22 Nec Corp Forecaster/encoder

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6862615B2 (en) 2018-11-16 2021-04-21 三菱電機株式会社 Attack detection device, attack detection method, and attack detection program
JP7290221B2 (en) 2019-09-30 2023-06-13 国立大学法人大阪大学 Remaining life prediction system, remaining life prediction device, and remaining life prediction program

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6154786A (en) * 1984-08-27 1986-03-19 Nec Corp Forecasting coding device
JPS6156590A (en) * 1984-08-28 1986-03-22 Nec Corp Forecaster/encoder
JPH0352718B2 (en) * 1984-08-28 1991-08-12 Nippon Electric Co

Also Published As

Publication number Publication date
JPS6148316B2 (en) 1986-10-23

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