JPS54141538A - Microprocessor system - Google Patents

Microprocessor system

Info

Publication number
JPS54141538A
JPS54141538A JP4922478A JP4922478A JPS54141538A JP S54141538 A JPS54141538 A JP S54141538A JP 4922478 A JP4922478 A JP 4922478A JP 4922478 A JP4922478 A JP 4922478A JP S54141538 A JPS54141538 A JP S54141538A
Authority
JP
Japan
Prior art keywords
data
address
instruction
accumulator
store
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4922478A
Other languages
Japanese (ja)
Other versions
JPS5856144B2 (en
Inventor
Hideo Tsuboi
Hiroshi Asami
Yutaka Hamano
Kinzo Takaba
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP53049224A priority Critical patent/JPS5856144B2/en
Publication of JPS54141538A publication Critical patent/JPS54141538A/en
Publication of JPS5856144B2 publication Critical patent/JPS5856144B2/en
Expired legal-status Critical Current

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  • Microcomputers (AREA)

Abstract

PURPOSE: To enable to deliver a lot of data in matching with the data line in the same timing, by using a part of a plurality of address lines as the data line and providing the data latch circuit.
CONSTITUTION: In using the 8-bit data bus and the 16-bit address bus, first, the LDA (load address) instruction allows the second write-in data to the accumulator 31 to store. The STA (store address) instruction moves the content W2 of the accumulator 31 to the external memory 32. The LDA instruction store the first write-in data W1. The address A of 8-bit is set to the external memory 34, and the address A and the data W2 are moved to the register 35 with the LDX (load X) instruction. The data W1 in the accumulator 33 and the data W2 in the register 35 are transferred to the latch 17 in the timing of the next STA instruction.
COPYRIGHT: (C)1979,JPO&Japio
JP53049224A 1978-04-27 1978-04-27 microprocessor system Expired JPS5856144B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53049224A JPS5856144B2 (en) 1978-04-27 1978-04-27 microprocessor system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53049224A JPS5856144B2 (en) 1978-04-27 1978-04-27 microprocessor system

Publications (2)

Publication Number Publication Date
JPS54141538A true JPS54141538A (en) 1979-11-02
JPS5856144B2 JPS5856144B2 (en) 1983-12-13

Family

ID=12824949

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53049224A Expired JPS5856144B2 (en) 1978-04-27 1978-04-27 microprocessor system

Country Status (1)

Country Link
JP (1) JPS5856144B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6111863A (en) * 1984-06-26 1986-01-20 Sharp Corp Microcomputer system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6111863A (en) * 1984-06-26 1986-01-20 Sharp Corp Microcomputer system

Also Published As

Publication number Publication date
JPS5856144B2 (en) 1983-12-13

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