JPS54132153A - Automatic equalizer circuit - Google Patents

Automatic equalizer circuit

Info

Publication number
JPS54132153A
JPS54132153A JP4001478A JP4001478A JPS54132153A JP S54132153 A JPS54132153 A JP S54132153A JP 4001478 A JP4001478 A JP 4001478A JP 4001478 A JP4001478 A JP 4001478A JP S54132153 A JPS54132153 A JP S54132153A
Authority
JP
Japan
Prior art keywords
signal
equalizer
peak value
timing
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4001478A
Other languages
Japanese (ja)
Inventor
Takashi Kihara
Satoshi Ikeuchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP4001478A priority Critical patent/JPS54132153A/en
Publication of JPS54132153A publication Critical patent/JPS54132153A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B3/00—Line transmission systems
    • H04B3/02—Details
    • H04B3/04—Control of transmission; Equalising
    • H04B3/06—Control of transmission; Equalising by the transmitted signal

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Filters And Equalizers (AREA)

Abstract

PURPOSE:To obtain the constant equalized waveform in an automatic way regardless of the change of the frequency characteristics of the transmission line by detecting the peak value of the timing component for the transmission signal and then controlling the variable equalizer with the control signal corresponding to the detected peak value. CONSTITUTION:In the digital transmission system, the signal transmitted through the transmission line is supplied to terminal 1 and then amplified through AGC amplifier to secure the constant average level. The output of amplifier 2 is applied to timing filter 3 as well as to fixed equalizer 6. Filter 3 is the BPF which uses the bit rate frequency as its central frequency and extracts the timing signal. This timing signal detects the peak value at peak detection circuit 4. The detected signal controls variable equalizer 5, and the signal supplied from equalizer 6 is then delivered through terminal 7 which is controlled so that the peak value based on the bit rate frequency component. Thus, the optimum equalized output can be obtained at terminal 7 regardless of the transmission characteristics by giving a proper control to equalizer 5.
JP4001478A 1978-04-05 1978-04-05 Automatic equalizer circuit Pending JPS54132153A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4001478A JPS54132153A (en) 1978-04-05 1978-04-05 Automatic equalizer circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4001478A JPS54132153A (en) 1978-04-05 1978-04-05 Automatic equalizer circuit

Publications (1)

Publication Number Publication Date
JPS54132153A true JPS54132153A (en) 1979-10-13

Family

ID=12569043

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4001478A Pending JPS54132153A (en) 1978-04-05 1978-04-05 Automatic equalizer circuit

Country Status (1)

Country Link
JP (1) JPS54132153A (en)

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