JPS54121625A - Memory multiplication system - Google Patents

Memory multiplication system

Info

Publication number
JPS54121625A
JPS54121625A JP2959278A JP2959278A JPS54121625A JP S54121625 A JPS54121625 A JP S54121625A JP 2959278 A JP2959278 A JP 2959278A JP 2959278 A JP2959278 A JP 2959278A JP S54121625 A JPS54121625 A JP S54121625A
Authority
JP
Japan
Prior art keywords
regions
input
internal memory
data
processor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2959278A
Other languages
Japanese (ja)
Inventor
Yukio Akai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP2959278A priority Critical patent/JPS54121625A/en
Publication of JPS54121625A publication Critical patent/JPS54121625A/en
Pending legal-status Critical Current

Links

Landscapes

  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE: To increase greatly the internal memory capacity by dividing the data region of the internal memory in the information processor using the central processor into plural units of regions and then selecting the divided regions with the input/output control order given from the processor.
CONSTITUTION: Internal memory 5 of information process part 1 contains program region 6 plus data region 7 divided into 71W7n. The order which is given from CPU2 as the input/output control signal to give addresses within the memory areas of data regions 71W7n is converted into the selector signal for regions 71W7n. Thus, the specified data region is selected. As a result, the acess is possible to the data regions up to 256 in case, for example, input/output devices 8W10 are not used regardless of the 8-bit structure of the input/output address bus. Accordingly, the capacity of the internal memory is increased, enhancing the cost performance.
COPYRIGHT: (C)1979,JPO&Japio
JP2959278A 1978-03-14 1978-03-14 Memory multiplication system Pending JPS54121625A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2959278A JPS54121625A (en) 1978-03-14 1978-03-14 Memory multiplication system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2959278A JPS54121625A (en) 1978-03-14 1978-03-14 Memory multiplication system

Publications (1)

Publication Number Publication Date
JPS54121625A true JPS54121625A (en) 1979-09-20

Family

ID=12280334

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2959278A Pending JPS54121625A (en) 1978-03-14 1978-03-14 Memory multiplication system

Country Status (1)

Country Link
JP (1) JPS54121625A (en)

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