JPS54113224A - Receiving buffer control system - Google Patents
Receiving buffer control systemInfo
- Publication number
- JPS54113224A JPS54113224A JP1985078A JP1985078A JPS54113224A JP S54113224 A JPS54113224 A JP S54113224A JP 1985078 A JP1985078 A JP 1985078A JP 1985078 A JP1985078 A JP 1985078A JP S54113224 A JPS54113224 A JP S54113224A
- Authority
- JP
- Japan
- Prior art keywords
- text
- buffer
- storing
- stored
- receiving buffer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Computer And Data Communications (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
- Small-Scale Networks (AREA)
- Communication Control (AREA)
Abstract
PURPOSE:To improve the usage efficiency of a receiving buffer by providing a number of unit buffers and using one unit for a text shorter than the unit buffer capacity and a number of connected units for a long text. CONSTITUTION:Receiving buffer RB is composed of a number of unit buffers UBB1 to B7 and table TB. Then, table TB is provided with means F1 indicating the usage state of UB1 means AR1 storing the start address, means F2 storing whether other UB's are connected or not, means AR2 storing the start address of the preceding connected UB and means BC storing the number of data stored in UB. Now, when the transmitted text length is shorter than the UB capacity, this text is stored in an idle UB, and the number of data is stored in part BC. Meanwhile, when the text length is longer than the UB length, this text is stored by connecting idle UB's. Thus, by dividing buffer RB and controlling it, it is possible to improve the usage efficiency of the buffer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1985078A JPS54113224A (en) | 1978-02-24 | 1978-02-24 | Receiving buffer control system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1985078A JPS54113224A (en) | 1978-02-24 | 1978-02-24 | Receiving buffer control system |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS54113224A true JPS54113224A (en) | 1979-09-04 |
JPS573098B2 JPS573098B2 (en) | 1982-01-20 |
Family
ID=12010715
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1985078A Granted JPS54113224A (en) | 1978-02-24 | 1978-02-24 | Receiving buffer control system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS54113224A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61272844A (en) * | 1985-05-29 | 1986-12-03 | Fujitsu Ltd | Collection and contol system for status information |
JPH02249024A (en) * | 1989-03-22 | 1990-10-04 | Nec Corp | Data transfer device |
US6831920B1 (en) | 1998-09-29 | 2004-12-14 | Fujitsu Limited | Memory vacancy management apparatus and line interface unit |
-
1978
- 1978-02-24 JP JP1985078A patent/JPS54113224A/en active Granted
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61272844A (en) * | 1985-05-29 | 1986-12-03 | Fujitsu Ltd | Collection and contol system for status information |
JPH02249024A (en) * | 1989-03-22 | 1990-10-04 | Nec Corp | Data transfer device |
US6831920B1 (en) | 1998-09-29 | 2004-12-14 | Fujitsu Limited | Memory vacancy management apparatus and line interface unit |
Also Published As
Publication number | Publication date |
---|---|
JPS573098B2 (en) | 1982-01-20 |
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