JPS54111725A - Error processing system in memory unit - Google Patents

Error processing system in memory unit

Info

Publication number
JPS54111725A
JPS54111725A JP1847278A JP1847278A JPS54111725A JP S54111725 A JPS54111725 A JP S54111725A JP 1847278 A JP1847278 A JP 1847278A JP 1847278 A JP1847278 A JP 1847278A JP S54111725 A JPS54111725 A JP S54111725A
Authority
JP
Japan
Prior art keywords
error
cpu
bit error
report
memory unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1847278A
Other languages
English (en)
Inventor
Tsutomu Yokoi
Takashi Tabei
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP1847278A priority Critical patent/JPS54111725A/ja
Publication of JPS54111725A publication Critical patent/JPS54111725A/ja
Pending legal-status Critical Current

Links

Landscapes

  • Detection And Correction Of Errors (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
JP1847278A 1978-02-22 1978-02-22 Error processing system in memory unit Pending JPS54111725A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1847278A JPS54111725A (en) 1978-02-22 1978-02-22 Error processing system in memory unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1847278A JPS54111725A (en) 1978-02-22 1978-02-22 Error processing system in memory unit

Publications (1)

Publication Number Publication Date
JPS54111725A true JPS54111725A (en) 1979-09-01

Family

ID=11972576

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1847278A Pending JPS54111725A (en) 1978-02-22 1978-02-22 Error processing system in memory unit

Country Status (1)

Country Link
JP (1) JPS54111725A (ja)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59154700A (ja) * 1983-02-23 1984-09-03 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション デ−タ処理システム
JPS63310045A (ja) * 1987-06-11 1988-12-19 Mitsubishi Electric Corp マイクロコンピユ−タ
CN105373443A (zh) * 2014-08-19 2016-03-02 三星电子株式会社 具有存储器系统体系结构的数据系统和数据读取方法
US10521113B2 (en) 2015-07-13 2019-12-31 Samsung Electronics Co., Ltd. Memory system architecture
US10824499B2 (en) 2014-08-19 2020-11-03 Samsung Electronics Co., Ltd. Memory system architectures using a separate system control path or channel for processing error information

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50117323A (ja) * 1974-02-28 1975-09-13
JPS50147630A (ja) * 1974-05-16 1975-11-26
JPS5169615A (en) * 1974-12-14 1976-06-16 Fujitsu Ltd Kiokusochino shogaitsuchiseigyohoshiki

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50117323A (ja) * 1974-02-28 1975-09-13
JPS50147630A (ja) * 1974-05-16 1975-11-26
JPS5169615A (en) * 1974-12-14 1976-06-16 Fujitsu Ltd Kiokusochino shogaitsuchiseigyohoshiki

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59154700A (ja) * 1983-02-23 1984-09-03 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション デ−タ処理システム
JPS63310045A (ja) * 1987-06-11 1988-12-19 Mitsubishi Electric Corp マイクロコンピユ−タ
CN105373443A (zh) * 2014-08-19 2016-03-02 三星电子株式会社 具有存储器系统体系结构的数据系统和数据读取方法
CN105373443B (zh) * 2014-08-19 2020-04-07 三星电子株式会社 具有存储器系统体系结构的数据系统和数据读取方法
US10824499B2 (en) 2014-08-19 2020-11-03 Samsung Electronics Co., Ltd. Memory system architectures using a separate system control path or channel for processing error information
US10521113B2 (en) 2015-07-13 2019-12-31 Samsung Electronics Co., Ltd. Memory system architecture

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