JPS54111230A - Input control system - Google Patents

Input control system

Info

Publication number
JPS54111230A
JPS54111230A JP1889778A JP1889778A JPS54111230A JP S54111230 A JPS54111230 A JP S54111230A JP 1889778 A JP1889778 A JP 1889778A JP 1889778 A JP1889778 A JP 1889778A JP S54111230 A JPS54111230 A JP S54111230A
Authority
JP
Japan
Prior art keywords
input
signal
processing
outputted
timing error
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1889778A
Other languages
Japanese (ja)
Other versions
JPS6118772B2 (en
Inventor
Hideyuki Takahashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP1889778A priority Critical patent/JPS54111230A/en
Publication of JPS54111230A publication Critical patent/JPS54111230A/en
Publication of JPS6118772B2 publication Critical patent/JPS6118772B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Input From Keyboards Or The Like (AREA)

Abstract

PURPOSE:To perform a high-reliability input information processing by detecting surely a timing error by a simple hardware constitution when information input intervals dependent upon the operation of input assignment elements are shorter than the processing time of input information. CONSTITUTION:Code information corresponding to encoder 102 is outputted by the operation of key K1 on a key mat. Meanwhile, signal ST is outputted from strobe generator circuit 103 on a basis of the signal of input detector circuit 101, and code information peculiar to keys K1 to Kn is stored in data input register 104. Meanwhile, signal ST is inputted to inverter 201 of timing error detector circuit 201. When the next key operation is performed before the input processing of data input register 104 is completed, FF 202 and 204 are set, and one-level timing error signal ERR is outputted from output terminal Q of FF 204. After that, FF 202 is cleared by outputting read signal R from processing control circuit 105 after the input processing, and FF 204 reads contents 0 of FF 202.
JP1889778A 1978-02-21 1978-02-21 Input control system Granted JPS54111230A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1889778A JPS54111230A (en) 1978-02-21 1978-02-21 Input control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1889778A JPS54111230A (en) 1978-02-21 1978-02-21 Input control system

Publications (2)

Publication Number Publication Date
JPS54111230A true JPS54111230A (en) 1979-08-31
JPS6118772B2 JPS6118772B2 (en) 1986-05-14

Family

ID=11984362

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1889778A Granted JPS54111230A (en) 1978-02-21 1978-02-21 Input control system

Country Status (1)

Country Link
JP (1) JPS54111230A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0196029U (en) * 1987-12-18 1989-06-26

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0196029U (en) * 1987-12-18 1989-06-26

Also Published As

Publication number Publication date
JPS6118772B2 (en) 1986-05-14

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